A Survey on Security Threats and Countermeasures in IEEE Test Standards

Emanuele Valea (1) , Mathieu da Silva (1) , Giorgio Di Natale (2) , Marie-Lise Flottes (1) , Bruno Rouzeyre (1)

1 TEST - Test and dEpendability of microelectronic integrated SysTems
2 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

The growth in complexity of Integrated Circuits (IC) is supported, amongst other factors, by the development of standardized test infrastructures. The feasibility of both end-ofmanufacturing and in-field tests heavily depends on the presence of these infrastructures that give detailed access to the IC. The standard test infrastructures are referred as IEEE Std. 1149.1 (JTAG), IEEE Std. 1500 and IEEE Std. 1687 (IJTAG). The security issues arising from the presence of these infrastructures have been fully exposed in the last two decades. This led to the publication of several practical attacks showing how a non-protected test infrastructure can end into the jeopardizing of the entire system. As a consequence, many countermeasures have been proposed. In this survey, we provide: (i) a taxonomy of the attacks that can be performed exploiting the standard test infrastructures; (ii) a taxonomy of countermeasures inspired by the kind of security primitives that are granted in each case.

Mots clés: Test standards; Testing vs security; Hardware security

Domaines: Micro et nanotechnologies/Microélectronique

Emanuele Valea, Mathieu da Silva, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Survey on Security Threats and Countermeasures in IEEE Test Standards. IEEE Design & Test, 2019, 36 (3), pp.95-116. ⟨10.1109/MDAT.2019.2899064⟩. ⟨hal-02166858⟩