I. Goodfellow, Deep Learning, 2016.

C. Poon and K. Zhou, Neuromorphic silicon neurons and largescale neural networks: challenges and opportunities, Frontiers in Neuroscience, vol.5, p.108, 2011.

T. N. Theis and H. P. Wong, The end of moore's law: A new beginning for information technology, Computing in Science & Engineering, vol.19, issue.2, pp.41-50, 2017.

C. Mead, Neuromorphic electronic systems, Proceedings of the IEEE, vol.78, issue.10, pp.1629-1636, 1990.

R. Serrano-gotarredona, CAVIAR: A 45k neuron, 5m synapse, 12g connects/s AER hardware sensory-processing-learning-actuating system for high-speed visual object recognition and tracking, IEEE Transactions on Neural Networks, vol.20, issue.9, pp.1417-1438, 2009.

G. Volanis, Toward silicon-based cognitive neuromorphic ICs-a survey, IEEE Design & Test, vol.33, issue.3, pp.91-102, 2016.

C. D. Schuman, A survey of neuromorphic computing and neural networks in hardware, 2017.

M. Valle, Analog VLSI implementation of artificial neural networks with supervised on-chip learning, Analog Integrated Circuits and Signal Processing, vol.33, pp.263-287, 2002.

S. Yu, Neuro-inspired computing with emerging nonvolatile memorys, Proceedings of the IEEE, vol.106, issue.2, pp.260-285, 2018.

L. , Neuromorphic computing -from robust hardware architectures to testing strategies, Proc. IFIP/IEEE International Conference on Very Large Scale Integration, pp.176-179, 2018.

M. L. Bushnell and V. D. , Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, 2000.

S. Mitra and E. J. Mccluskey, Which concurrent error detection scheme to choose ?, Proc. IEEE International Test Conference, pp.985-994, 2000.

G. Roberts, An Introduction to Mixed-Signal IC Test and Measurement, 2011.

H. Stratigopoulos, Machine learning applications in IC testing, Proc. IEEE European Test Symposium, 2018.

D. Maliuk, Analog neural network design for RF built-in selftest, Proc. IEEE International Test Conference, 2010.
URL : https://hal.archives-ouvertes.fr/hal-00560465

S. Pandey, Error resilient neuromorphic networks using checker neurons, Proc. IEEE International Symposium on On-Line Testing And Robust System Design, pp.135-138, 2018.

J. J. Zhang, Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator, Proc. IEEE VLSI Test Symposium, 2018.

M. Liu, Design of fault-tolerant neuromorphic computing systems, Proc. IEEE European Test Symposium, 2018.

A. P. Johnson, Homeostatic fault tolerance in spiking neural networks: A dynamic hardware perspective, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.65, issue.2, pp.687-699, 2018.

W. Maass, Networks of spiking neurons: The third generation of neural network models, Neural Networks, vol.10, issue.9, pp.1659-1671, 1997.

G. Indiveri, Neuromorphic silicon neuron circuits, Frontiers in Neuroscience, vol.5, p.73, 2011.
URL : https://hal.archives-ouvertes.fr/hal-00597675

B. W. Connors and M. J. Gutnik, Intrinsic firing patterns of diverse neocortical neurons, Trends Neurosciences, vol.13, issue.3, pp.99-104, 1990.

J. H. Wijekoon and P. Dudek, Compact silicon neuron circuit with spiking and burtsing behaviour, Neural Networks, vol.21, issue.4, pp.524-534, 2016.

E. M. Izhikevich, Simple model of spiking neurons, IEEE Transactions on Neural Networks, vol.14, issue.6, pp.1569-1572, 2003.

S. Sunter, Using mixed-signal defect simulation to close the loop between design and test, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.63, issue.12, pp.2313-2322, 2016.

B. Esen, Effective DC fault models and testing approach for open defects in analog circuits, Proc. IEEE International Test Conference, 2016.