Self-Testing Analog Spiking Neuron Circuit

Sarah Ali El-Sayed; Luis Camuñas-Mesa; Bernabe Linares-Barranco; Haralampos-G. Stratigopoulos

Self-Testing Analog Spiking Neuron Circuit

Sarah Ali El-Sayed ¹ Luis Camuñas-Mesa ² Bernabe Linares-Barranco ² Haralampos-G. Stratigopoulos ¹

1 CIAN - Circuits Intégrés Numériques et Analogiques

LIP6

2 IMSE-CNM CSIC - Instituto de Microelectrónica de Sevilla

Abstract : Hardware-implemented neural networks are foreseen to play an increasing role in numerous applications. In this paper, we address the problem of post-manufacturing test and self-test of hardware-implemented neural networks. In particular, we propose a self-testable version of a spiking neuron circuit. The self-test wrapper is a compact circuit composed of a low-precision ramp generator and a small digital block. The self-test principle is demonstrated on a spiking neuron circuit design in 0.35µm CMOS technology.

Document type :

Conference papers

Domain :

Engineering Sciences [physics] / Micro and nanotechnologies/Microelectronics

Computer Science [cs] / Artificial Intelligence [cs.AI]

Computer Science [cs] / Computer Aided Engineering

Computer Science [cs] / Modeling and Simulation

Engineering Sciences [physics] / Electronics

Computer Science [cs] / Embedded Systems

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https://hal.archives-ouvertes.fr/hal-02164969
Contributor : Haralampos Stratigopoulos <>
Submitted on : Tuesday, June 25, 2019 - 2:52:59 PM
Last modification on : Friday, July 5, 2019 - 3:26:03 PM

SMACD_2019_paper_91.pdf

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