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Self-Testing Analog Spiking Neuron Circuit
Abstract : Hardware-implemented neural networks are foreseen to play an increasing role in numerous applications. In this paper, we address the problem of post-manufacturing test and self-test of hardware-implemented neural networks. In particular, we propose a self-testable version of a spiking neuron circuit. The self-test wrapper is a compact circuit composed of a low-precision ramp generator and a small digital block. The self-test principle is demonstrated on a spiking neuron circuit design in 0.35µm CMOS technology.
Cited literature [26 references]
https://hal.archives-ouvertes.fr/hal-02164969
Contributor : Haralampos Stratigopoulos Connect in order to contact the contributor
Submitted on : Tuesday, June 25, 2019 - 2:52:59 PM
Last modification on : Sunday, June 26, 2022 - 2:39:01 AM
Contributor : Haralampos Stratigopoulos Connect in order to contact the contributor
Submitted on : Tuesday, June 25, 2019 - 2:52:59 PM
Last modification on : Sunday, June 26, 2022 - 2:39:01 AM
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SMACD_2019_paper_91.pdf
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