Self-Testing Analog Spiking Neuron Circuit

Sarah Ali El-Sayed (1) , Luis A Camuñas-Mesa (2) , Bernabé Linares-Barranco (2) , Haralampos-G. Stratigopoulos (1)

1 CIAN - Circuits Intégrés Numériques et Analogiques
2 IMSE-CNM - Instituto de Microelectrónica de Sevilla

Hardware-implemented neural networks are foreseen to play an increasing role in numerous applications. In this paper, we address the problem of post-manufacturing test and self-test of hardware-implemented neural networks. In particular, we propose a self-testable version of a spiking neuron circuit. The self-test wrapper is a compact circuit composed of a low-precision ramp generator and a small digital block. The self-test principle is demonstrated on a spiking neuron circuit design in 0.35µm CMOS technology.

Domaines: Micro et nanotechnologies/Microélectronique; Intelligence artificielle [cs.AI]; Ingénierie assistée par ordinateur; Modélisation et simulation; Electronique; Systèmes embarqués

Sarah Ali El-Sayed, Luis A Camuñas-Mesa, Bernabé Linares-Barranco, Haralampos-G. Stratigopoulos. Self-Testing Analog Spiking Neuron Circuit. 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2019), Jul 2019, Lausanne, Switzerland. pp.81-84, ⟨10.1109/SMACD.2019.8795234⟩. ⟨hal-02164969⟩