Functional Verification of Hardware Dividers using Algebraic Model
Résumé
Division is one of the most complex arithmetic operations
to implement and its hardware implementation requires a
thorough verification on the gate level. Dividers circuits are difficult
to prove using standard Boolean verification methods, such as
equivalence checking and SAT, as they require "bit-blasting" onto
bit-level netlists. Other verification approaches, such as theorem
provers, concentrate mostly on proving the correctness of the
division algorithm and the resulting architectures. However, the
verification of low-level hardware implementation of dividers
has received only a limited attention. This paper addresses the
problem of formally verifying gate-level divider circuits using an
algebraic model. In contrast to standard approaches using SAT
or equivalence checking, our method verifies whether the gatelevel
divider circuit actually performs a division, without a need
for a reference design. The method extends algebraic rewriting
technique, successfully used to prove other arithmetic circuits, to
dividers.