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Sub-nanosecond delay CMOS Active Gate Driver for Closed-Loop dv/dt Control of GaN Transistors

Abstract : This paper presents an AGD (active gate driver) implemented with a low voltage CMOS technology to control the dv/dt sequence of low voltage (100V) and high voltage (650V) GaN power transistors. Such an AGD can control and reduce the dv/dt of fast switching GaN devices with a reduced impact on switching losses. In the case of both low voltage and high voltage GaN fast switching transistors, such an AGD must have a total response time lower than 1ns. Therefore, introducing a feedback loop to control the dv/dt requires a specific design with a very high bandwidth (550MHz). Moreover, probing the vDS voltage and its derivative is quite challenging, as the voltage level is higher than the low voltage gate driver supply. The purpose of this work is to optimize a low voltage CMOS AGD with fully integrated functions, and implement such a solution in GaN-based power converters. Keywords-Active gate driver, GaN, switching analysis, dv/dt, EMI, power electronics, ASIC for power ic.
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Contributor : Frédéric Richardeau <>
Submitted on : Saturday, November 7, 2020 - 3:18:22 PM
Last modification on : Thursday, November 19, 2020 - 3:30:24 PM

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Bau Plinio, Marc Cousineau, Bernardo Cogo, Frederic Richardeau, Vinnac Sébastien, et al.. Sub-nanosecond delay CMOS Active Gate Driver for Closed-Loop dv/dt Control of GaN Transistors. 31st IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD), May 2019, Shanghai, China. ⟨10.1109/ispsd.2019.8757693⟩. ⟨hal-02157332⟩

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