Vertical termination filled with adequate dielectric for SiC devices in HVDC applications

T. Nguyen-Bui (1, 2) , Mihai Lazar (1, 2) , Jean-Louis Augé (1) , Hervé Morel (1, 2) , L. Phung (1, 2) , Dominique Planson (1, 2)

1 EE - Ampère, Département Energie Electrique
2 INSA Lyon - Institut National des Sciences Appliquées de Lyon

To fully achieve the performance which SiC power devices potentially have, it is necessary to reduce the electric field crowding effect taking place at the junction edges. So far, numerous techniques have been adapted to improve the breakdown voltage mainly under the planar technology, using for example, guard ring, field plate (FP), semi-insulating polycystalline (SIPOS), junction termination extension (JTE), 3D RESURF... However for high voltage devices, these techniques have the drawback of consuming large areas. Recently, thanks to the advancement in the Micro Electro Mechanical Systems (MEMS) process technology, the deep trench termination (DT2) technique becomes an appropriate choice for future high voltage power device. The edge termination design used for improving the breakdown voltage (VBR) and reducing drastically the chip area comparing to the above conventional structures. This concept has been already demonstrated in Si technology.

Domaines: Energie électrique

T. Nguyen-Bui, Mihai Lazar, Jean-Louis Augé, Hervé Morel, L. Phung, et al.. Vertical termination filled with adequate dielectric for SiC devices in HVDC applications. International Conference on Silicon Carbide and Related Materials 2015 (ICSCRM 2015), Oct 2015, Giardini Naxos, Italy. ⟨hal-02138529⟩