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4H-SiC P-N junctions realized by VLS for JFET lateral structures

Abstract : Lateral JFET transistors have been fabricated with N and P-type channels tentatively integrated monolithically on the same SiC wafer. Buried P+ SiC layers grown by Vapor-Liquid-Solid (VLS) selective epitaxy were utilized as source and drain for the P-JFET and as gate for the N-JFET. The ohmicity of the contacts, both on VLS grown P+ and ion implanted N+ layers, has been confirmed by Transfer Length Method (TLM) measurements. A premature leakage current is observed on the P/N junction created directly by the P+ VLS gate layer, probably due to imperfect VLS (P+) / CVD (N+) SiC interface.
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Submitted on : Sunday, May 19, 2019 - 4:19:51 PM
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Selsabil Sejil, Farah Laariedh, Mihai Lazar, Davy Carole, Christian Brylinski, et al.. 4H-SiC P-N junctions realized by VLS for JFET lateral structures. ECSCRM'14, Sep 2014, Grenoble, France. pp.TU-P-61. ⟨hal-02133686⟩



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