4H-SiC P-N junctions realized by VLS for JFET lateral structures

Selsabil Sejil (1, 2) , Farah Laariedh (2, 3) , Mihai Lazar (2, 3) , Davy Carole (1) , Christian Brylinski (1) , Dominique Planson (2, 3) , Gabriel Ferro (1) , Christophe Raynaud (2, 3) , Hervé Morel (2, 3)

1 LMI - Laboratoire des Multimatériaux et Interfaces
2 EE - Ampère, Département Energie Electrique
3 INSA Lyon - Institut National des Sciences Appliquées de Lyon

Lateral JFET transistors have been fabricated with N and P-type channels tentatively integrated monolithically on the same SiC wafer. Buried P+ SiC layers grown by Vapor-Liquid-Solid (VLS) selective epitaxy were utilized as source and drain for the P-JFET and as gate for the N-JFET. The ohmicity of the contacts, both on VLS grown P+ and ion implanted N+ layers, has been confirmed by Transfer Length Method (TLM) measurements. A premature leakage current is observed on the P/N junction created directly by the P+ VLS gate layer, probably due to imperfect VLS (P+) / CVD (N+) SiC interface.

Mots clés: Junction Field Effect Transistor (JFET); VLS epitaxial growth; JFET; TLM; roughness

Domaines: Energie électrique

Selsabil Sejil, Farah Laariedh, Mihai Lazar, Davy Carole, Christian Brylinski, et al.. 4H-SiC P-N junctions realized by VLS for JFET lateral structures. ECSCRM'14, Sep 2014, Grenoble, France. pp.TU-P-61. ⟨hal-02133686⟩