Ternary computers: The setun and the setun 70, Perspectives on Soviet and Russian Computing, pp.74-80, 2011. ,
URL : https://hal.archives-ouvertes.fr/hal-01568401
Ranging in the ieee 802.15. 4a standard, IEEE Annual Wireless and Microwave Technology Conference, pp.1-5, 2006. ,
Ternary convolutional codes for ternary phase shift keying, IEEE Communications Letters, vol.20, issue.9, pp.1709-1712, 2016. ,
Adaptive scalable texture compression, Proceedings of the Fourth ACM SIGGRAPH/Eurographics conference on High-Performance Graphics, pp.105-114, 2012. ,
Polarization state of a biphoton: Quantum ternary logic, Physical Review A, vol.60, issue.6, p.4209, 1999. ,
Binary to modified trinary number system conversion and vice-versa for optical super computing, Natural Computing, vol.9, issue.4, pp.917-934, 2010. ,
Ternary weight networks, 2016. ,
Scalable high-performance architecture for convolutional ternary neural networks on fpga, 27th International Conference on Field Programmable Logic and Applications, pp.1-7, 2017. ,
URL : https://hal.archives-ouvertes.fr/hal-01563763
High-efficiency convolutional ternary neural networks with custom adder trees and weight compression, ACM Trans. Reconfigurable Technol. Syst, vol.11, issue.3, pp.1-15, 2018. ,
URL : https://hal.archives-ouvertes.fr/hal-01686718
Multilevel logic synthesis, Proceedings of the IEEE, vol.78, issue.2, pp.264-300, 1990. ,
Multi-level logic minimization using implicit don't cares, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.7, issue.6, pp.723-740, 1988. ,
Exact algorithms for output encoding, state assignment, and four-level boolean minimization, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.10, issue.1, pp.13-27, 1991. ,
Optimal state assignment for finite state machines, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.4, issue.3, pp.269-285, 1985. ,
Synthesis and optimization of digital circuits, 1994. ,
An output encoding problem and a solution technique, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.18, issue.6, pp.761-768, 1999. ,
Multilevel logic optimization of very high complexity circuits, Proceedings of the European Design Automation conference, pp.14-19, 1994. ,
Espresso-signature: A new exact minimizer for logic functions, IEEE Transactions on Very Large Scale Integration Systems, vol.1, issue.4, pp.432-440, 1993. ,
The hungarian method for the assignment problem, Naval Research Logistics Quarterly, vol.2, pp.83-97, 1955. ,
Minimization of boolean functions, Bell system technical Journal, vol.35, issue.6, pp.1417-1444, 1956. ,
A 2.9tops/w deep convolutional neural network soc in fd-soi 28nm for intelligent embedded systems, 2017 IEEE International Solid-State Circuits Conference, pp.238-239, 2017. ,
Imagenet classification with deep convolutional neural networks, Advances in neural information processing systems, pp.1097-1105, 2012. ,
Dark memory and accelerator-rich system optimization in the dark silicon era, IEEE Design & Test, vol.34, issue.2, pp.39-50, 2017. ,