V TH -Hysteresis and Interface States Characterisation in SiC Power MOSFETs with Planar and Trench Gate

Besar Asllani (1, 2) , Alberto Castellazzi (3) , Oriol Aviño Salvado (1, 2) , Asad Fayyaz (3) , Hervé Morel (2, 1) , Dominique Planson (2, 1)

1 EE - Ampère, Département Energie Electrique
2 INSA Lyon - Institut National des Sciences Appliquées de Lyon
3 Power Electronics Machines and Control (PEMC) Group

This paper contributes to investigations on the threshold-voltage (VTH) hysteresis in SiC power MOSFETs. Such effect is of relevance mainly for sub-threshold operation of the devices, but needs to be told apart from stress-related VTH-drift phenomena for technology maturity and reliability validation goals. Important differences exist in commercially available devices, particularly in relation to their gate technology, planar or trench, the latter also showing a marked temperature dependence of the hysteretic range. Based on the experimental characterization of the interface capacitance and charge, this paper puts forward a methodology for determining the types of traps affecting the various devices, with the aim of contributing a tool to assist driving of technological maturity in future generation devices. This paper also shows the potential of capacitance hysteresis measurement to the estimation of the distribution of interface.

Mots clés: Planar gate; Threshold voltage hysteresis; interface traps; SiC MOSFETs; Trench gate

Domaines: Energie électrique

Besar Asllani, Alberto Castellazzi, Oriol Aviño Salvado, Asad Fayyaz, Hervé Morel, et al.. V TH -Hysteresis and Interface States Characterisation in SiC Power MOSFETs with Planar and Trench Gate. IRPS, Mar 2019, Monterey, CA, United States. ⟨10.1109/IRPS.2019.8720612⟩. ⟨hal-02099781⟩