Counterfeit integrated circuits: A rising threat in the global semiconductor supply chain, Proceedings of the IEEE, vol.102, issue.8, pp.1207-1228, 2014. ,
Hardware Trojan attacks: Threat Analysis and Countermeasures, Proceedings of the IEEE, vol.102, issue.8, pp.1229-1247, 2014. ,
A VLSI Design Flow for Secure SideChannel Attack Resistant ICs, Automation & Test in Europe, pp.58-63, 2005. ,
URL : https://hal.archives-ouvertes.fr/hal-00181821
Fault Injection Attacks on Cryptographic Devices: Theory, Practice, and Countermeasures, Proceedings of the IEEE, vol.100, issue.11, pp.3056-3076, 2012. ,
URL : https://hal.archives-ouvertes.fr/hal-01110932
The State-of-the-Art in Semiconductor Reverse Engineering, IEEE/ACM Design Automation Conference, pp.333-338, 2011. ,
Security Aspects of Analog and Mixed-Signal Circuits, IEEE International Mixed-Signal Testing Workshop, 2016. ,
Trusted analog/mixed-signal/RF ICs: A survey and a perspective, IEEE Design & Test, vol.34, issue.6, pp.63-76, 2017. ,
Challenges and Opportunities in Analog and Mixed Signal (AMS) Integrated Circuit (IC) Security, Journal of Hardware and Systems Security, vol.2, issue.1, pp.15-32, 2018. ,
Provably-secure logic locking: From theory to practice, ACM/SIGSAC Conference on Computer & Communications Security, pp.1601-1618, 2017. ,
Towards secure analog designs: A secure sense amplifier using memristors, IEEE Computer Society Annual Symposium on VLSI, 2014. ,
Protecting analog circuits with parameter biasing obfuscation, IEEE Latin American Test Symposium, 2017. ,
Thwarting analog IC piracy via combinational locking, IEEE International Test Conference, 2017. ,
, MAX36051: DeepCover Security Manager with 128 Bytes of Nonimprinting Memory
Active hardware metering for intellectual property protection and security, USENIX Security Symposium, 2007. ,
Physical unclonable functions and applications: A tutorial, Proceedings of the IEEE, vol.102, issue.8, pp.1126-1141, 2014. ,
Design of on-chip lightweight sensors for effective detection of recycled ICs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.22, issue.5, pp.1016-1029, 2014. ,
Ending Piracy of Integrated Circuits, IEEE Computer, vol.43, issue.10, pp.30-38, 2010. ,
Fault Analysis-Based Logic Encryption, IEEE Transactions on Computers, vol.64, issue.2, pp.410-424, 2015. ,
On Improving the Security of Logic Locking, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.35, issue.9, pp.1411-1424, 2016. ,
Evaluating the Security of Logic Encryption Algorithms, IEEE International Symposium on Hardware Oriented Security and Trust, pp.137-143, 2015. ,
SARLock: SAT Attack Resistant Logic Locking, IEEE International Symposium on Hardware Oriented Security and Trust, pp.236-241, 2016. ,
DOI : 10.1109/hst.2016.7495588
Mitigating SAT Attack on Logic Locking, International Conference on Cryptographic Hardware and Embedded Systems, pp.127-146, 2016. ,
Removal Attacks on Logic Locking and Camouflaging Techniques, IEEE Transactions on Emerging Topics in Computing, 2017. ,
SARLock: SAT attack resistant logic locking, IEEE International Symposium on Hardware Oriented Security and Trust, 2016. ,
AppSAT: Approximately Deobfuscating Integrated Circuits, IEEE International Symposium on Hardware Oriented Security and Trust, pp.95-100, 2017. ,
Double dip: Re-evaluating security of logic encryption algorithms, Cryptology ePrint Archive, 2017. ,
A 2.4 GHz ISM-band highly digitized receiver based on a variable gain LNA and a subsampled Sigma-Delta ADC, Analog Integrated Circuits and Signal Processing, vol.95, issue.2, pp.259-270, 2018. ,
URL : https://hal.archives-ouvertes.fr/hal-01802453