Impact of Complex-Logic Cell Layout on the Single-Event Transient Sensitivity

Ygor Quadros de Aguiar (1, 2) , Frédéric Wrobel (1, 2) , Jean-Luc Autran (3) , Paul Leroux (4) , Frédéric Saigné (2, 1) , Antoine Touboul (2, 1) , Vincent Pouget (2, 1)

1 RADIAC - Radiations et composants
2 IES - Institut d’Electronique et des Systèmes
3 IM2NP - Institut des Matériaux, de Microélectronique et des Nanosciences de Provence
4 KU Leuven - Catholic University of Leuven = Katholieke Universiteit Leuven

The design methodology based on standard cells is widely used in a broad range of VLSI applications. Further, several optimization algorithms can be employed to address different constraints such as power consumption or reliability. This work evaluates the implications of the usage of complex-logic cells from a 45 nm Standard-Cell library to the Single-Event Transient sensitivity under heavy ions. Results show that even though a reduction in the layout area is obtained when adopting complex-logic gates, a slight reduction in the total sensitive area of the circuit is observed. Moreover, the effectiveness of logical masking can be suppressed, leading to a higher SET cross-section.

Mots clés: Complex-logic gate; Heavy ions; Logical Masking; Monte-Carlo simulation; Single-Event Transient

Domaines: Electronique

Ygor Quadros de Aguiar, Frédéric Wrobel, Jean-Luc Autran, Paul Leroux, Frédéric Saigné, et al.. Impact of Complex-Logic Cell Layout on the Single-Event Transient Sensitivity. IEEE RADECS2018, Sep 2018, Goteborg, Sweden. ⟨hal-02086422⟩