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Journal articles
Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators
Abstract : Domain-specific acceleration is now a "must" for all the computing spectrum, going from high performance computing to embedded systems. Unfortunately, system specialization is by nature a nightmare from the design productivity perspective. Nevertheless, in contexts where kernels to be accelerated are intrinsically streaming oriented, the combination of dataflow models of computation with Coarse-Grained Reconfigurable (CGR) architectures can be particularly handful. In this paper we introduce a novel methodology to assemble and characterize virtually reconfigurable accelerators based on dataflow and functional programming principles, capable of addressing design productivity issues for CGR accelerators. The main advantage of the proposed methodology is accurate IP-level latency predictability improving Design Space Exploration (DSE) when compared to state-of-the-art High-Level Synthesis (HLS).
Cited literature [18 references]
https://hal.archives-ouvertes.fr/hal-02062002
Contributor : Maxime Pelcat <>
Submitted on : Friday, March 8, 2019 - 2:43:41 PM
Last modification on : Wednesday, February 26, 2020 - 4:04:55 PM
Document(s) archivé(s) le : Monday, June 10, 2019 - 9:25:41 AM
Contributor : Maxime Pelcat <>
Submitted on : Friday, March 8, 2019 - 2:43:41 PM
Last modification on : Wednesday, February 26, 2020 - 4:04:55 PM
Document(s) archivé(s) le : Monday, June 10, 2019 - 9:25:41 AM
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