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FPGA based accelerator for visual features detection

François Brenot 1 Philippe Fillatreau 2, * Jonathan Piat 1
* Corresponding author
1 LAAS-RAP - Équipe Robotique, Action et Perception
LAAS - Laboratoire d'analyse et d'architecture des systèmes
Abstract : In the context of obstacle detection and tracking for a vision-based ADAS (Advanced Driver Assistance System), one mandatory task is vehicle localization. Vision-based SLAM (Simultaneous Localization and Mapping) proposes to solve this problem by combining the estimation of the vehicle state (local-isation : position and orientation) and an incremental modelling of the environment using a perception module (feature detection and matching) in images acquired using one camera or more. Such a perception module requires an important computational load that highly affects the latency and the throughput of the system. Our goal is to implement the SLAM functionality on a low power consumption mixed hardware and software architecture (using a co-design approach) based on a Xilinx Zynq FPGA. This device includes logic cells that allows to speed-up the perception tasks to meet the real-time constraint of an ADAS. In this paper, we present the implementation of two hardware components : a FAST (Features from Accelerated Segment Test) features detector and a parametrizable corner refinement module (Non Maxima Suppression-NMS).
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https://hal.archives-ouvertes.fr/hal-01300912
Contributor : Jonathan Piat <>
Submitted on : Wednesday, February 22, 2017 - 3:05:22 PM
Last modification on : Friday, January 10, 2020 - 9:10:11 PM
Long-term archiving on: : Tuesday, May 23, 2017 - 1:02:21 PM

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François Brenot, Philippe Fillatreau, Jonathan Piat. FPGA based accelerator for visual features detection. International Workshop IEEE Electronics, Control, Measurement, Signals and their application to Mechatronics (ECMSM), Jun 2015, Liberec, Czech Republic. ⟨10.1109/ECMSM.2015.7208697⟩. ⟨hal-01300912⟩

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