Impact of strain on access resistance in planar and nanowire CMOS devices

Rémy Berthelon (1, 2, 3) , F. Andneu (1) , F. Triozon (1) , M. Cassé (1) , L. Bourdet (4) , G. Ghibaudo (5) , D. Rideau (2) , Y.M. Niquet (4) , S. Barraud (1) , P. Nguyen (1) , C. Le Royer (1) , J. Lacord (1) , C. Tabone (1) , O. Rozeau (1) , D. Dutartre (2) , Alain Claverie (3) , E. Josse (2) , F. Arnaud (2) , M. Vinet (1)

1 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
2 ST-CROLLES - STMicroelectronics [Crolles]
3 CEMES - Centre d'élaboration de matériaux et d'études structurales
4 LSIM - Laboratory of Atomistic Simulation
5 IMEP-LAHC - Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation

We fabricated and in-depth characterized advanced planar and nanowire CMOS devices, strained by the substrate (sSOI or SiGe channel) and by the process (CESL, SiGe source/drain). We have built a novel access resistance (R ACC ) extraction procedure, which enables us to clearly evidence the strong impact of back-bias and strain on R acc (-21% for 4 V V B and -53% for -1GPa stress on pMOS FDSOI). This is in agreement with Non-Equilibrium-Green-Functions (NEGF) simulations. This RAcc(strain) dependence has been introduced into SPICE, leading to +6% increase of the RO frequency under ε n/p =0.8%/-0.5% strain, compared to the state-of-the-art model. It is thus mandatory for predictive benchmarking and optimized IC designs.

Domaines: Micro et nanotechnologies/Microélectronique

Rémy Berthelon, F. Andneu, F. Triozon, M. Cassé, L. Bourdet, et al.. Impact of strain on access resistance in planar and nanowire CMOS devices. 2017 IEEE Symposium on VLSI Technology, Jun 2017, Kyoto, Japan. pp.T224-T225, ⟨10.23919/VLSIT.2017.7998180⟩. ⟨hal-02050220⟩