A New Mapping Methodology for Coarse-Grained Programmable Systolic Architectures

Elias Barbudo (1, 2) , Eva Dokladalova (1, 2) , Thierry Grandpierre (2, 1) , Laurent George (1, 2)

1 ESIEE Paris
2 LIGM - Laboratoire d'Informatique Gaspard-Monge

Coarse-grained programmable systolic hardware architectures are designed to meet hard time constraints and provide high-performance computing. They consist of a set of programmable hardware resources with directed interconnections between them. The level of complexity of these architectures limits their reusability. An automated mapping methodology is required to add a reusability value to these architectures. In this work, we present a new list-scheduling based mapping methodology for coarse-grained programmable ar-chitectures. We use a Directed Acyclic Graph to express the task and data dependency of the application as well as hardware resources organization. We demonstrate that our approach can map different applications to a complex architecture such as Morphological Co-Processor Unit and provide latency estimation of the final implementation. This approach could be considered as base for design space exploration and optimisation.

Mots clés: FPGA; Mapping methodology; pipeline-based hardware; scheduling

Domaines: Architectures Matérielles [cs.AR]; Traitement des images [eess.IV]; Traitement du signal et de l'image [eess.SP]

Elias Barbudo, Eva Dokladalova, Thierry Grandpierre, Laurent George. A New Mapping Methodology for Coarse-Grained Programmable Systolic Architectures. 22nd International Workshop on Software and Compilers for Embedded Systems (SCOPES 2019), May 2019, St Goar, Germany. ⟨10.1145/3323439.3323982⟩. ⟨hal-02013560⟩