A New Mapping Methodology for Coarse-Grained Programmable Systolic Architectures

Abstract : Coarse-grained programmable systolic hardware architectures are designed to meet hard time constraints and provide high-performance computing. They consist of a set of programmable hardware resources with directed interconnections between them. The level of complexity of these architectures limits their reusability. An automated mapping methodology is required to add a reusability value to these architectures. In this work, we present a new list-scheduling based mapping methodology for coarse-grained programmable ar-chitectures. We use a Directed Acyclic Graph to express the task and data dependency of the application as well as hardware resources organization. We demonstrate that our approach can map different applications to a complex architecture such as Morphological Co-Processor Unit and provide latency estimation of the final implementation. This approach could be considered as base for design space exploration and optimisation.
Complete list of metadatas

Cited literature [20 references]  Display  Hide  Download

https://hal.archives-ouvertes.fr/hal-02013560
Contributor : Eva Dokladalova <>
Submitted on : Friday, April 19, 2019 - 12:34:37 PM
Last modification on : Saturday, May 18, 2019 - 12:30:08 AM

File

scopes2019 (1).pdf
Files produced by the author(s)

Identifiers

Collections

Citation

Elias Barbudo, Eva Dokladalova, Thierry Grandpierre, Laurent George. A New Mapping Methodology for Coarse-Grained Programmable Systolic Architectures. 22nd International Workshop on Software and Compilers for Embedded Systems (SCOPES 2019), May 2019, St Goar, Germany. ⟨10.1145/3323439.3323982⟩. ⟨hal-02013560⟩

Share

Metrics

Record views

59

Files downloads

126