Low-Latency LDPC Decoding Achieved by Code and Architecture Co-Design

Abstract : A novel low-density parity-check decoder architecture is presented that can achieve a high data throughput while retaining the flexibility to decode a wide range of quasi-cyclic codes. The proposed architecture allows to combine multiple message-update schedules, providing an additional degree of freedom to jointly optimize the code and decoder architecture. Protograph-based code constructions are introduced that exploit this added degree of freedom in order to maximize data throughput, and that are also optimized to reduce the complexity of the required parallel data accesses.For some examples and under an ideal pipeline speedup assumption, the proposed architecture and code designs reduce decoding latency by a factor of $3.2\times$ compared to a decoder using a strict sequential schedule.
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Submitted on : Wednesday, February 6, 2019 - 5:08:37 PM
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  • HAL Id : hal-02009983, version 1


Elsa Dupraz, Francois Leduc Primeau, François Gagnon. Low-Latency LDPC Decoding Achieved by Code and Architecture Co-Design. ISTC 2018 : International Symposium on Turbo Codes & Iterative Information Processing, Dec 2018, Hong Kong, Hong Kong SAR China. ⟨hal-02009983⟩



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