Multi Bit Upset detection and correction based on self-robust Non-Volatile C-element
Résumé
For embedded systems in harsh environments, a radiation robust circuit design is still an open challenge. As circuits become more and more complex and CMOS processes get denser and smaller, their immunity towards particle strikes decreases drastically so that soft errors remain a serious concern even in terrestrial environment. Due to its inherent resistance to radiation effects as well as its inborn non- volatility, Spin-Transfer-Torque-based magnetic tunnel junction (STT-MTJ) is considered as a very promising candidate for high reliability electronics. Nevertheless, specific hardening techniques must be investigated since MTJs are still vulnerable to radiations due to their peripheral circuits.
A new design solution combining the well-known hardening technique of Dual Modular Redundancy and a robust state-holding CMOS-MTJs hybrid design is presented in this poster. It is hinged on the first radiation hardened STT-MTJ based C-element. This innovative hybrid VLSI structure allows the detection and correction of multi event upset (MEU) acting both as errors filter and as storage checkpoint. Moreover, it addresses the issue of undesirable magnetization reversal in the MTJ storage layer due to the surrounding CMOS counterpart. A physics-based MTJ 40nm compact model and 28 nm FDSOI technology are used for circuit design. Simulations were run with standard electrical simulator under usual CAD tool platform. Errors injected into the sensitive nodes of the circuit shown a non-volatile error occurrence drastically reduced and a radiation tolerance capability up to 330 fC equivalent injected charge.