A computational study of van der Waals tunnel transistors: Fundamental aspects and design challenges

Jiang Cao (1) , Demetrio Logoteta (1) , Sibel Ozkaya (2) , Blanca Biel (3) , Alessandro Cresti (1) , Marco Pala (1) , David Esseni (4)

1 IMEP-LAHC - Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation
2 Department of Physics [Aksaray]
3 UGR - Universidad de Granada = University of Granada
4 Università degli Studi di Udine - University of Udine [Italie]

We propose a model Hamiltonian for van der Waals tunnel transistors relying on a few physical parameters that we calibrate against DFT band structure calculations. This approach allowed us to develop a fully three-dimensional (3-D) NEGF based simulator and to investigate fundamental and design aspects related to van der Waals tunnel transistors, such as: (a) area and edge tunneling components, and scaling with device area; (b) impact of top gate alignment and back-oxide thickness on the device performance; (c) influence of inelastic phonon scattering on the device operation and sub-threshold swing; (d) benchmarking of switching energy and delay.

Domaines: Micro et nanotechnologies/Microélectronique

Jiang Cao, Demetrio Logoteta, Sibel Ozkaya, Blanca Biel, Alessandro Cresti, et al.. A computational study of van der Waals tunnel transistors: Fundamental aspects and design challenges. 2015 IEEE International Electron Devices Meeting (IEDM), Dec 2015, Washington, United States. pp.12.5.1 - 12.5.4, ⟨10.1109/IEDM.2015.7409684⟩. ⟨hal-01967913⟩