DLL-Enhanced PLL Frequency Synthesizer with Two Feedback Loops and Body Biasing for Noise Cleaning

Yann Deval (1) , Andrés Asprilla , David Cordova (2) , Herve Lapuyade (1) , Francois Rivet (1)

1 IMS - Laboratoire de l'intégration, du matériau au système
2 UFRGS - Universidade Federal do Rio Grande do Sul [Porto Alegre]

This paper presents the relevant aspects of the design of an ultra-low-power frequency synthesizer based on the combination of two feedback loops, a Phase-Locked Loop (PLL) acting together with a Delay-Locked Loop (DLL) to perform fine and coarse tuning of the desired output frequency, respectively. The objective of the circuit is to achieve a power consumption lower than 100 µA to generate a 2.5 GHz output frequency, improving the poor phase-noise of ring oscillators with the usage of the DLL circuit as an auxiliary feedback loop to cancel the phase noise and adjusting the VCO frequency through the body bias feature, available in the 28 nm FDSOI technology from STMicroelectronics.

Domaines: Micro et nanotechnologies/Microélectronique

Yann Deval, Andrés Asprilla, David Cordova, Herve Lapuyade, Francois Rivet. DLL-Enhanced PLL Frequency Synthesizer with Two Feedback Loops and Body Biasing for Noise Cleaning. IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Oct 2018, Qingdao, China. ⟨hal-01964932⟩