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Aggressive Memory Speculation in HW/SW Co-Designed Machines

Simon Rokicki 1 Erven Rohou 2 Steven Derrien 1
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
2 PACAP - Pushing Architecture and Compilation for Application Performance
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : Single-ISA heterogeneous systems (such as ARM big.LITTLE) are an attractive solution for embedded platforms as they expose performance/energy trade-offs directly to the operating system. Recent works have demonstrated the ability to increase their efficiency by using VLIW cores, supported through Dynamic Binary Translation (DBT) to maintain the illusion of a single-ISA system. However, VLIW cores cannot rival with Outof- Order (OoO) cores when it comes to performance, mainly because they do not use speculative execution. In this work, we study how it is possible to use memory dependency speculation during the DBT process. Our approach enables fine-grained speculation optimizations thanks to a combination of hardware and software. Our results show that our approach leads to a geo-mean speed-up of 10% at the price of a 7% area overhead.
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Submitted on : Sunday, December 2, 2018 - 5:27:50 PM
Last modification on : Friday, July 10, 2020 - 4:01:39 PM
Long-term archiving on: : Sunday, March 3, 2019 - 2:12:01 PM


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Simon Rokicki, Erven Rohou, Steven Derrien. Aggressive Memory Speculation in HW/SW Co-Designed Machines. DATE 2019 - 22nd IEEE/ACM Design, Automation and Test in Europe, Mar 2019, Florence, Italy. pp.332-335, ⟨10.23919/DATE.2019.8715010⟩. ⟨hal-01941876⟩



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