S. Das, Energy-efficient and reliable 3D Network-on-Chip (NoC): Architectures and optimization algorithms, Proc. IEEE/ACM Inter. Conf. on Computer-Aided Design (ICCAD), pp.1-6, 2016.

M. Valadbeigi, F. Safaei, and B. Pourshirazi, An Energy-Efficient Reconfigurable NoC Architecture with RF-Interconnects, Proc. Euromicro Conf. on Digital System Design, pp.489-496, 2013.

L. Guo, W. Hou, and P. Guo, Designs of 3D mesh and torus optical Network-on-Chips: Topology, optical router and routing module, China Communications, vol.14, issue.5, pp.17-29, 2017.

Z. Chen and H. Gu, A Power Efficient and Compact Optical Interconnect for Network-on-Chip, IEEE Computer Archi. Letters, vol.13, issue.1, pp.5-8, 2014.

A. Mineo and M. Palesi, Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures, IEEE Trans. on VLSI Systems, vol.24, issue.4, pp.1535-1545, 2016.

A. Karkar and T. Mak, A survey of emerging interconnects for onchip efficient multicast and broadcast in many-cores, IEEE Circuits and Systems Magazine, vol.16, issue.1, pp.58-72, 2016.

A. Ganguly and K. Chang, Performance evaluation of wireless networks on chip architectures, Proc. Inter. Symp. on Quality Electronic Design, pp.350-355, 2009.

P. P. Pande and A. Ganguly, Hybrid wireless network on chip: A new paradigm in multi-core design, Proc. Inter. Workshop on NoC Archi, pp.71-76, 2009.

D. Ditomaso and A. Kodi, A-WiNoC: Adaptive Wireless Networkon-Chip Architecture for Chip Multiprocessors, IEEE Trans. on Parallel and Distributed Systems, vol.26, issue.12, pp.3289-3302, 2015.

A. Kayi, Adaptive Cache Coherence Mechanisms with ProducerConsumer Sharing Optimization for Chip Multiprocessors, IEEE Trans. on Computers, vol.64, issue.2, pp.316-328, 2015.

A. Asaduzzaman, K. K. Chidella, and D. Vardha, An Energy-Efficient Directory Based Multicore Architecture with Wireless Routers to Minimize the Communication Latency, IEEE Trans. on Parallel and Distributed Systems, vol.28, issue.2, pp.374-385, 2017.

R. G. Kim and W. Choi, Wireless NoC for VFI-Enabled Multicore Chip Design: Performance Evaluation and Design Trade-Offs, IEEE Trans. on Computers, vol.65, issue.4, pp.1323-1336, 2016.

D. W. Matolak and S. Kaya, Channel modeling for wireless networkson-chips, IEEE Comm. Magazine, vol.51, issue.6, pp.180-186, 2013.

M. O. Agyeman and Q. T. Vien, An Analytical Channel Model for Emerging Wireless Networks-on-Chip, Proc. IEEE Inter. Conf. on Comp. Science and Engineering, pp.9-15, 2016.

A. Ganguly and P. Pande, A Unified Error Control Coding Scheme to Enhance the Reliability of a Hybrid Wireless Network-on-Chip, Proc. IEEE Inter. Symp. on Defect and Fault Tolerance in VLSI and Nanotech. Systems, pp.277-285, 2011.

J. J. Lin, H. T. Wu, and Y. Su, Communication Using Antennas Fabricated in Silicon Integrated Circuits, IEEE Journal of Solid-State Circuits, vol.42, issue.8, pp.1678-1687, 2007.

Y. P. Zhang and Z. M. Chen, Propagation Mechanisms of Radio Waves Over Intra-Chip Channels With Integrated Antennas: FrequencyDomain Measurements and Time-Domain Analysis, IEEE Trans. on Antennas and Propagation, vol.55, issue.10, pp.2900-2906, 2007.

K. Kim, W. Bomstad, and K. O. Kenneth, A plane wave model approach to understanding propagation in an intra-chip communication system, Proc. IEEE Antennas and Propag, vol.2, pp.166-169, 2001.

Y. P. Zhang, M. Sun, and W. Fan, Performance of integrated antennas on silicon substrates of high and low resistivities up to 110 GHz for wireless interconnects, Microwave and Optical Tech. Letters, vol.48, issue.2, pp.302-305, 2006.

A. Hajimiri, mm-Wave Silicon ICs: Challenges and Opportunities, Proc. IEEE Custom Integrated Circuits Conf, pp.741-747, 2007.

A. Babakhani and X. Guan, A 77-GHz Phased-Array Transceiver With On-Chip Antennas in Silicon: Receiver and Antennas, IEEE Journal of Solid-State Circuits, vol.41, issue.12, pp.2795-2806, 2006.

K. Kim and H. Yoon, On-chip wireless interconnection with integrated antennas, Proc. Inter. Electron Devices Meeting (IEDM), pp.485-488, 2000.

X. Yu, A 1.2-pJ/bit 16-Gb/s 60-GHz OOK Transmitter in 65nm CMOS for Wireless Network-On-Chip, IEEE Trans. on Microwave Theory and Techniques, vol.62, issue.10, pp.2357-2369, 2014.
URL : https://hal.archives-ouvertes.fr/hal-00479027

X. Yu and H. Rashtian, An 18.7-Gb/s 60-GHz OOK Demodulator in 65-nm CMOS for Wireless Network-on-Chip, IEEE Trans. on Circuits and Systems I: Regular Papers, vol.62, issue.3, pp.799-806, 2015.

X. Yu, Architecture and design of multichannel millimeter-wave wireless noc, IEEE Design Test, vol.31, issue.6, pp.19-28, 2014.

N. Reiskarimian, A CMOS Passive LPTV Nonmagnetic Circulator and Its Application in a Full-Duplex Receiver, IEEE Journal of Solid-State Circuits, vol.52, issue.5, pp.1358-1372, 2017.

. Proakis, Digital Communications 5th Edition, 2007.

A. Vidapalapati and V. Vijayakumaran, NoC architectures with adaptive Code Division Multiple Access based wireless links, Proc. IEEE Inter. Symp. on Circuits and Systems, pp.636-639, 2012.

S. L. , 22.3 A 20GHz-BW 6b 10GS/s 32mW time-interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI technology, Proc. IEEE Inter. Solid-State Circuits Conf. (ISSCC), pp.382-383, 2014.

R. Clarke and M. R. Leroy, 140 Gb/s Serializer Using Clock Doublers in 90 nm SiGe Technology, IEEE Journal of Solid-State Circuits, vol.50, issue.11, pp.2703-2713, 2015.

S. A. Mohammed, S. A. Ibrahim, and S. E. Habib, 6-Gb/s serial link transceiver for NoCs, Proc. IEEE Inter. Conf. on Electronics, Circuits, and Systems, pp.425-428, 2015.

N. F. Kiyani, P. Harpe, and G. Dolmans, Performance analysis of ook modulated signals in the presence of adc quantization noise, IEEE Vehicular Technology Conference, pp.1-5, 2012.

K. Duraisamy and Y. Xue, Multicast-aware high-performance wireless network-on-chip architectures, IEEE Trans. onVLSI Systems, vol.25, issue.3, pp.1126-1139, 2017.