, Aeronautical Radio Inc. ARINC 664, vol.7, 2005.

L. Abdallah, J. Ermont, J. Scharbarg, and C. Fraboul, Towards a mixed NoC/AFDX architecture for avionics applications, IEEE 13th International Workshop on Factory Communication Systems, 2017.
URL : https://hal.archives-ouvertes.fr/hal-02001631

L. Abdallah, J. Mathieu-jan, C. Ermont, and . Fraboul, Wormhole networks properties and their use for optimizing worst case delay analysis of many-cores, 10th IEEE International Symposium on Industrial Embedded Systems (SIES), pp.59-68, 2015.
URL : https://hal.archives-ouvertes.fr/cea-01836859

L. Abdallah, J. Mathieu-jan, C. Ermont, and . Fraboul, Reducing the contention experienced by real-time core-to-I/O flows over a Tilera-like Network on Chip, Real-Time Systems (ECRTS), pp.86-96, 2016.
URL : https://hal.archives-ouvertes.fr/cea-01838135

H. Ayed, J. Ermont, J. L. Scharbarg, and C. Fraboul, Towards a unified approach for worst-case analysis of Tilera-like and KalRay-like NoC architectures, 2016 IEEE World Conference on Factory Communication Systems (WFCS), pp.1-4, 2016.
URL : https://hal.archives-ouvertes.fr/hal-02001640

H. Charara, J. Scharbarg, J. Ermont, and C. Fraboul, Methods for bounding end-to-end delays on an AFDX network, Proc of the 18th Euromicro Conf. on Real-Time Systems (ECRTS). Dresde, pp.193-202, 2006.

I. Ilog-cplex, V12. 1: User's Manual for CPLEX. International Business Machines Corporation, vol.46, p.157, 2009.

B. Dupont-de-dinechin, D. Van-amstel, M. Poulhiès, and G. Lager, Time-critical Computing on a Single-chip Massively Parallel Processor, Proc. of the Conf. on Design, Automation & Test in Europe (DATE'14), vol.97, pp.1-97, 2014.
URL : https://hal.archives-ouvertes.fr/hal-01090449

E. Luiz-de-souza and . Carvalho, Ney Laert Vilar Calazans, and Fernando Gehm Moraes, Design & Test of Computers, vol.27, pp.26-35, 2010.

R. Do, 178C. Software considerations in airborne systems and equipment certification, 2011.

M. Fattah, M. Daneshtalab, P. Liljeberg, and J. Plosila, Smart hill climbing for agile dynamic mapping in many-core systems, Proc. of the 50th Annual Design Automation Conference, p.39, 2013.

M. Fattah, M. Ramirez, M. Daneshtalab, P. Liljeberg, and J. Plosila, CoNA: Dynamic application mapping for congestion reduction in many-core systems, 30th Intl. Conf. on Computer Design (ICCD, pp.364-370, 2012.

T. Ferrandiz, F. Frances, and C. Fraboul, Using Network Calculus to compute end-to-end delays in SpaceWire networks, SIGBED Review, vol.8, pp.44-47, 2011.

J. Kang and S. Park, Algorithms for the variable sized bin packing problem, European Journal of Operational Research, vol.147, pp.365-372, 2003.

S. Martello and P. Toth, Knapsack Problems, J, 1990.

P. Mohapatra, Wormhole routing techniques for directly connected muti-computer systems, ACM Computer Survey (CSUR), vol.30, issue.3, pp.374-410, 1998.

V. Nélis, P. Meumeu-yomsi, L. M. Pinho, J. C. Fonseca, M. Bertogna et al., The Challenge of Time-Predictability in Modern Many-Core Architectures, 14th Intl. Workshop on Worst-Case Execution Time Analysis. Madridr, Spain, pp.63-72, 2014.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards et al., On-Chip Interconnection Architecture of the Tile Processor, IEEE Micro, vol.27, pp.15-31, 2007.

C. Zimmer and F. Mueller, Low contention mapping of real-time tasks onto tilepro 64 core processors, 18th Real-Time and Embedded Technology and Applications Symposium (RTAS, pp.131-140, 2012.