Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip

T. Kempf (1, 2, 3) , V. Della Marca (2) , L. Baron (1) , F. Maugain (1) , F. La Rosa (1) , S. Niel (1) , A. Regnier (1) , Jean-Michel Portal (2) , P. Masson (3)

1 ST-ROUSSET - STMicroelectronics [Rousset]
2 IM2NP - Institut des Matériaux, de Microélectronique et des Nanosciences de Provence
3 Polytech'Lab - Laboratoire de Polytech Nice-Sophia

The reliability requirements of Flash memory become more and more challenging. Flash memory technology development needs test chips to allow large statistical studies and a product-like approach. In this paper, we present a methodology of bitmap analysis to extract and follow the intrinsic and extrinsic parameters of a 40nm eFlash technology during ramp-up. This methodology is, first, based on analog bitmap acquisition on 512kB test chip, followed by correction of spatial variabilities like peripheral circuits' influences, array organization impacts and process-induced effects, to extract supplementary cell electrical parameters such as threshold voltage, transconductance or programing window. Finally, such an analysis tool enhances the advantageous properties of a test chip, its large memory cell statistics and its product-like organization, to give more reliable data. It yields more information about intrinsic cell technology weaknesses and the best way to tackle them when integrated at product level.

Domaines: Micro et nanotechnologies/Microélectronique

T. Kempf, V. Della Marca, L. Baron, F. Maugain, F. La Rosa, et al.. Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip. IEEE International Reliability Physics Symposium (IRPS 2018), Mar 2018, Burlingame, CA, United States. ⟨10.1109/IRPS.2018.8353642⟩. ⟨hal-01900771⟩