Efficient architecture for Reed Solomon block turbo code

Erwan Piriou (1) , Christophe Jego (2, 1) , Patrick Adde (1) , Raphaël Le Bidan (3) , Michel Jezequel (1)

1 ELEC - Département Electronique
2 Lab-STICC_TB_CACS_IAS
3 SC - Département Signal et Communications

Reed-Solomon codes are block-based error correcting codes with a wide range of applications in digital communications and storage. Recently, block turbo codes using Reed-Solomon component codes have been introduced. This was motivated by the highest code rate property of Reed-Solomon codes and their efficiency for burst error correction. In fact, the main advantage of Reed-Solomon block turbo codes is for high code rate applications. For these applications, the code length and consequently the decoder complexity are smaller than for usual Bose-Chaudhuri-Hocquenghem block turbo codes. This paper presents a block turbo decoder architecture using Reed-Solomon component codes. Our elementary soft input soft output decoder is dedicated to Reed-Solomon codes (31, 29, 3) with single error correction power. To the authors' knowledge, this is the first published architecture implementing this type of decoder. Experimentation has been done on a Stratix-based NIOS development board

Mots clés: Reed-Solomon code; VLSI; Block turbo code

Domaines: Electronique; Traitement du signal et de l'image [eess.SP]

Erwan Piriou, Christophe Jego, Patrick Adde, Raphaël Le Bidan, Michel Jezequel. Efficient architecture for Reed Solomon block turbo code. ISCAS 2006 : IEEE International Symposium on Circuits And Systems, May 2006, Kos, Greece. pp.3682 - 3685, ⟨10.1109/ISCAS.2006.1693426⟩. ⟨hal-01876239⟩