An Energy-Efficient Integrated Programmable Array Accelerator and Compilation flow for Near-Sensor Ultra-low Power Processing

Satyajit Das 1, 2 Kevin Martin 1 Davide Rossi 2 Philippe Coussy 1 Luca Benini 2, 3
1 Lab-STICC_UBS_CACS_MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
Abstract : In this paper we give a fresh look to Coarse Grained Reconfigurable Arrays (CGRAs) as ultra-low power accelerators for near-sensor processing. We present a general-purpose Integrated Programmable-Array accelerator (IPA) exploiting a novel architecture, execution model, and compilation flow for application mapping that can handle kernels containing complex control flow, without the significant energy overhead incurred by state of the art predication approaches. To optimize the performance and energy efficiency, we explore the IPA architecture with special focus on shared memory access, with the help of the flexible compilation flow presented in this paper. We achieve a maximum energy gain of 2×, and performance gain of 1.33× and 1.8× compared with state of the art partial and full predication techniques, respectively. The proposed accelerator achieves an average energy efficiency of 1617 MOPS/mW operating at 100MHz, 0.6V in 28nm UTBB FD-SOI technology, over a wide range of near-sensor processing kernels, leading to an improvement up to 18×, with an average of 9.23× (as well as a speed-up up to 20.3×, with an average of 9.7×) compared to a core specialized for ultra-low power near-sensor processing.
Type de document :
Article dans une revue
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2018, pp.1 - 1. 〈10.1109/TCAD.2018.2834397〉
Liste complète des métadonnées

Littérature citée [22 références]  Voir  Masquer  Télécharger

https://hal.archives-ouvertes.fr/hal-01828604
Contributeur : Kevin Martin <>
Soumis le : mardi 3 juillet 2018 - 12:01:03
Dernière modification le : dimanche 15 juillet 2018 - 01:01:37
Document(s) archivé(s) le : lundi 1 octobre 2018 - 12:36:17

Fichier

IPA-TCAD18.pdf
Fichiers produits par l'(les) auteur(s)

Identifiants

Citation

Satyajit Das, Kevin Martin, Davide Rossi, Philippe Coussy, Luca Benini. An Energy-Efficient Integrated Programmable Array Accelerator and Compilation flow for Near-Sensor Ultra-low Power Processing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2018, pp.1 - 1. 〈10.1109/TCAD.2018.2834397〉. 〈hal-01828604〉

Partager

Métriques

Consultations de la notice

87

Téléchargements de fichiers

53