Analytical study of complementary memristive synchronous logic gates

Jean-Michel Portal , M. Moreau (1) , Marc Bocquet , Hassen Aziza (2) , D. Deleruyelle (2) , Christophe Muller (3) , Y. Zhang (4) , E. Deng , J.O O Klein , Damien Querlioz (5) , D. Ravelosona (5) , C. Chappert (5) , W.S. S Zhao , M. Portal (2)

1 LPTL - Laboratoire de Physique Théorique des Liquides
2 IM2NP - Institut des Matériaux, de Microélectronique et des Nanosciences de Provence
3 IPBS - Institut de pharmacologie et de biologie structurale
4 State Key Laboratory of Transient Optics and Photonics,
5 IEF - Institut d'électronique fondamentale

—This paper describes an analytical study of synchronous logic gate design based on hybrid structure with MOS and resistive switching non-volatile memories (RS-NVMs). This type of structure allows ultra-low power consumption during power down, while often-used data are saved in RS-NVM cells. The parallel data sensing achieves low-power and fast computation time. The logic gate construction theory, from Boolean equation to hybrid MOS/RS-NVM tree, is deeply detailed. Read and write design guideline, regarding RS-NVM and MOS resistance balance are investigated. Practical implementation is given through transient simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the concept by using CMOS 40 nm design kit and memory compact models.

Mots clés: Low-Power design; synchronous logic gate; Resistive Switching; complementary cell

Domaines: Sciences de l'ingénieur [physics]

Jean-Michel Portal, M. Moreau, Marc Bocquet, Hassen Aziza, D. Deleruyelle, et al.. Analytical study of complementary memristive synchronous logic gates. 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Jul 2013, Brooklyn, France. ⟨10.1109/NanoArch.2013.6623047⟩. ⟨hal-01827052⟩