Design exploration methodology for memristor-based spiking neuromorphic architectures with the Xnet event-driven simulator

O. Bichler (1) , D. Roclin , C. Gamrat (1) , D. Querlioz (2)

1 LIST (CEA) - Laboratoire d'Intégration des Systèmes et des Technologies
2 IEF - Institut d'électronique fondamentale

—We introduce an event-based methodology, and its accompanying simulator (" Xnet ") for memristive nanodevice-based neuromorphic hardware, which aims to provide an intermediate modeling level, between low-level hardware description languages and high-level neural networks simulators used primarily in neurosciences. This simulator was used to establish several results on Spike-Timing-Dependent Plasticity (STDP) modeling and implementation with Resistive RAM (RRAM), Conductive Bridge RAM (CBRAM) and Phase-Change Memory (PCM) type of memristive nanodevices. We present several simulation case studies that illustrate the event-based simulation strategies that we implemented, including unsupervised features extraction and Monte Carlo simulations. A discussion comparing event-based and fixed time-step simulation is included as well, and gives some metrics to guide the choice between the two depending on the application to simulate.

Domaines: Sciences de l'ingénieur [physics]

O. Bichler, D. Roclin, C. Gamrat, D. Querlioz. Design exploration methodology for memristor-based spiking neuromorphic architectures with the Xnet event-driven simulator. 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Jul 2013, Brooklyn New York, United States. ⟨10.1109/NanoArch.2013.6623029⟩. ⟨hal-01827049⟩