SEE error-rate evaluation of an application implemented in COTS Multi/Many-core processors
Résumé
This work evaluates the error-rate of a memorybound application implemented in different COTS multi-core and many-core processors. To achieve this goal, two quantitative experiments are performed: fault-injection campaigns and radiation ground testing. In addition, the paper proposes an approach for predicting the application error-rate by combining the results issued from both types of experiments. The usefulness of the approach is illustrated by three case-studies implemented in processors having different manufacturing technology and architecture: 45 nm SOI Freescale P2041 Quad-core processor, 65nm CMOS Adapteva Epiphany multi-core processor, and 28nm CMOS Kalray MPPA-256 many-core processor. The reliability of the processors for avionics is obtained from their experimental error-rate extrapolated to avionic altitudes. Reliability curves are plotted for observing the prediction accuracy. A comparison of the Failure in Time of the selected processors shows that the greater SEE vulnerability of CMOS technology compared to the SOI one can be compensated with the implementation of effective EDACs. These protection mechanisms allow the use of CMOS devices having huge memory capacity in applications operating in severe radiation environments.
