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Data level parallelism for H264/AVC baseline intra-prediction chain on MPSoC

Abstract : Currently, higher resolutions and faster frame rates are more and more demanded in real time video application. Consequently, encoder complexity and performance are the main penalties for such requirements. The emerging Multiprocessor System on Chip (MPSoC) architecture is a promising way for following the evolving video encoding applications, which can overcome the limitation of real-time processing with a single processor. Thus parallel computing for H.264/AVC encoder on multiprocessor is becoming a major research point that can resolve real time constraints. We contribute to this challenge by proposing MPSoC architecture for the intra prediction module, which is an important part of the H.264/AVC video encoder, using data level parallelism (DLP) approach. In this paper, we present an efficient partitioning of data for parallel processing for intra prediction; this approach is tested and evaluated on an open platform for virtual prototyping (SoCLiB). Experimental results show a gain of 74% in encoding speed when using four processors, and enabling minimum memory size and surface of MPSoC. Furthermore, our results highlight the relationship between the number of processors and the encoding run time.
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Contributor : Nejmeddine Bahri <>
Submitted on : Tuesday, May 22, 2018 - 2:13:06 PM
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Nidhameddine Belhadj, Najmeddine Bahri, M. Ali Ben Ayed, Zied Marrakchi, Habib Mehrez. Data level parallelism for H264/AVC baseline intra-prediction chain on MPSoC. 2013 10th International Multi-Conference on Systems, Signals & Devices (SSD), Mar 2013, Hammamet, Tunisia. ⟨10.1109/SSD.2013.6564040⟩. ⟨hal-01797203⟩



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