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Buffer-Aware Worst-Case Timing Analysis of Wormhole NoCs Using Network Calculus

Abstract : Abstract—Conducting worst-case timing analyses for wormhole Networks-on-chip (NoCs) is a fundamental aspect to guarantee real-time requirements, but it is known to be a challenging issue due to complex congestion patterns that can occur. In that respect, we introduce in this paper a new buffer-aware timing analysis of wormhole NoCs based on Network Calculus. Our main idea consists in considering the flows serialization phenomena along the path of a flow of interest (f.o.i), by paying the bursts of interfering flows only at the first convergence point, and refining the interference patterns for the f.o.i accounting for the limited buffer size. Moreover, we aim to handle such an issue for wormhole NoCs, implementing a fixed priority-preemptive arbitration of Virtual Channels (VCs), that can be assigned to an arbitrary number of traffic classes with different priority levels, i.e. VC sharing, and each traffic class may contain an arbitrary number of flows, i.e. priority sharing. It is worth noting that such characteristics cover a large panel of wormhole NoCs. The derived delay bounds are analyzed and compared to available results of existing approaches, based on Scheduling Theory as well as Compositional Performance Analysis (CPA). In doing this, we highlight a noticeable enhancement of the delay bounds tightness in comparison to CPA approach, and the inherent safe bounds of our proposal in comparison to Scheduling Theory approaches. Finally, we perform experiments on a manycore platform, to confront our timing analysis predictions to experimental data and assess its tightness.
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Submitted on : Tuesday, May 15, 2018 - 5:13:51 PM
Last modification on : Friday, May 18, 2018 - 10:02:54 AM
Long-term archiving on: : Monday, September 24, 2018 - 8:43:34 PM


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  • HAL Id : hal-01792736, version 1
  • OATAO : 19912


Frédéric Giroudot, Ahlem Mifdaoui. Buffer-Aware Worst-Case Timing Analysis of Wormhole NoCs Using Network Calculus. 2018 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Apr 2018, Porto, Portugal. pp. 1-12. ⟨hal-01792736⟩



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