, A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.408-412, 2016.
DOI : 10.1109/TVLSI.2015.2407370
URL : https://hal.archives-ouvertes.fr/in2p3-00021508
, A near-threshold 480 MHz 78uW all-digital PLL with a bootstrapped DCO Solid-State Circuits, IEEE Journal, vol.48, issue.11, pp.2805-2814, 2013.
DOI : 10.1109/jssc.2013.2280409
, A 20-to-1000MHz +/-14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS, 2014 IEEE International Solid- State Circuits Conference Digest of Technical Papers (ISSCC), pp.272-273, 2014.
, A fast-locking all-digital phase locked loop in 90nm CMOS for Gigascale systems, 2014 IEEE International Symposium on Circuits and Systems (ISCAS), pp.1134-1137, 2014.
DOI : 10.1109/ISCAS.2014.6865340
, A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique, IEEE Journal of Solid-State Circuits, vol.50, issue.1, pp.68-80, 2015.
DOI : 10.1109/JSSC.2014.2348311
, A Fine-Grain Variation-Aware Dynamic <formula formulatype="inline"><tex Notation="TeX">${\rm Vdd}$</tex></formula>-Hopping AVFS Architecture on a 32 nm GALS MPSoC, IEEE Journal of Solid-State Circuits, vol.49, issue.7, pp.1475-1486, 2014.
DOI : 10.1109/JSSC.2014.2317137
, A 28nm FD-SOI standard cell 0.6???1.2V open-loop frequency multiplier for low power SoC clocking, 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pp.1206-1209, 2016.
DOI : 10.1109/ISCAS.2016.7527463
URL : https://hal.archives-ouvertes.fr/hal-01434957
, A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp.129-132, 2016.
DOI : 10.1109/ASSCC.2016.7844152
URL : https://hal.archives-ouvertes.fr/in2p3-00018209
, A 2.7pJ/cycle 16MHz SoC with 4.3nW power-off ARM Cortex-M0+ core in 28nm FD-SOI, ESSCIRC 2017, 43rd IEEE European Solid State Circuits Conference
DOI : 10.1109/ESSCIRC.2017.8094550
URL : https://hal.archives-ouvertes.fr/hal-00604529