High density emerging resistive memories: What are the limits?
Résumé
With the saturation of the Flash memory technologies scaling under the 20nm nodes, new technology opportunities are explored by both industrial and academic research teams. Resistive switching memories are today seen as the most promising replacement candidate for both embedded (NOR) and stand-alone (NAND) flash memories. The native Back-End-of-Line (BEoL) integration enabled by the RRAM technologies opens the way for new 3D architectures such as crosspoint or Vertical-RRAM, and triggers the development of novel BEoL selection devices. These architectures bring new design challenges, for instance, sneaking currents through unselected bitcells (SneakPaths), voltage drop along deeply scaled (< 50nm) metal lines (IRdrop) and peripheral circuitry overhead. In this paper, we introduce two physical IRdrop models for crosspoint and Vertical-RRAM architectures. We also introduce a peripheral circuitry model for crosspoint architecture. Using these models, we show that both periphery overhead and IRdrop limit the crosspoint architecture under 50nm of half pitch.