A Faithful Binary Circuit Model with Adversarial Noise

Matthias Függer 1, 2, 3, 4 Jürgen Maier 5 Robert Najvirt 5 Thomas Nowak 6 Ulrich Schmid 5
4 MEXICO - Modeling and Exploitation of Interaction and Concurrency
LSV - Laboratoire Spécification et Vérification [Cachan], ENS Cachan - École normale supérieure - Cachan, Inria Saclay - Ile de France, CNRS - Centre National de la Recherche Scientifique : UMR8643
6 ParSys - LRI - Systèmes parallèles (LRI)
LRI - Laboratoire de Recherche en Informatique
Abstract : Accurate delay models are important for static and dynamic timing analysis of digital circuits, and mandatory for formal verification. However, Függer et al. [IEEE TC 2016] proved that pure and inertial delays, which are employed for dynamic timing analysis in state-of-the-art tools like ModelSim, NC-Sim and VCS, do not yield faithful digital circuit models. Involution delays, which are based on delay functions that are mathematical involutions depending on the previous-output-to-input time offset, were introduced by Függer et al. [DATE'15] as a faithful alternative (that can easily be used with existing tools). Although involution delays were shown to predict real signal traces reasonably accurately, any model with a deterministic delay function is naturally limited in its modeling power. In this paper, we thus extend the involution model, by adding non-deterministic delay variations (random or even adversarial), and prove analytically that faithfulness is not impaired by this generalization. Albeit the amount of non-determinism must be considerably restricted to ensure this property, the result is surprising: the involution model differs from non-faithful models mainly in handling fast glitch trains, where small delay shifts have large effects. This originally suggested that adding even small variations should break the faithfulness of the model, which turned out not to be the case. Moreover, the results of our simulations also confirm that this generalized involution model has larger modeling power and, hence, applicability.
Type de document :
Communication dans un congrès
DATE 2018 - Design, Automation and Test in Europe Conference and Exhibition, Mar 2018, Dresden, Germany. 〈10.23919/DATE.2018.8342219〉
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Soumis le : mardi 20 mars 2018 - 13:26:43
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Matthias Függer, Jürgen Maier, Robert Najvirt, Thomas Nowak, Ulrich Schmid. A Faithful Binary Circuit Model with Adversarial Noise. DATE 2018 - Design, Automation and Test in Europe Conference and Exhibition, Mar 2018, Dresden, Germany. 〈10.23919/DATE.2018.8342219〉. 〈hal-01738254〉



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