Hardware Implementation and Performance Analysis of Resource Efficient Probabilistic Hard Decision LDPC Decoders

Abstract : The Gallager B (GaB), among the hard-decision class of Low-Density-Parity-Check (LDPC) algorithms, is an ideal candidate for designing a high-throughput decoder hardware. However, GaB suffers from poor error-correction performance. We introduce a Probabilistic GaB (PGaB) algorithm that disturbs the decisions made during the decoding iterations randomly with a probability value determined based on experimental studies. We propose a heuristic that switches the decoding from GaB to PGaB after certain number of iterations, and show that our heuristic reduces the average iteration count by up to 62% compared to GaB. We evaluate the hardware performance and resource requirement trends of PGaB over three quasi cyclic codes using the Xilinx Virtex-6 Field Programmable Gate Array (FPGA). We extend this analysis to performance comparison over our implementations of Gradient Descent Bit Flipping (GDBF) and Probabilistic Gradient Descent Bit Flipping (PGDBF) algorithms for each code studied in this paper. We achieve up to four orders of magnitude better error correction performance than the GaB with less than 1% loss in throughput performance. Our heuristic consistently results with an improvement in maximum operational clock rate across all codes compared to the GDBF and PGDBF
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https://hal.archives-ouvertes.fr/hal-01727259
Contributeur : Fakhreddine Ghaffari <>
Soumis le : vendredi 9 mars 2018 - 08:32:59
Dernière modification le : jeudi 3 mai 2018 - 15:18:05

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Burak Unal, Ali Akoglu, Fakhreddine Ghaffari, Bane Vasic. Hardware Implementation and Performance Analysis of Resource Efficient Probabilistic Hard Decision LDPC Decoders. IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, 2018, 〈10.1109/TCSI.2018.2815008〉. 〈hal-01727259〉

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