Hardware Implementation and Performance Analysis of Resource Efficient Probabilistic Hard Decision LDPC Decoders
Résumé
The Gallager B (GaB), among the hard-decision class of Low-Density-Parity-Check (LDPC) algorithms, is an ideal candidate
for designing a high-throughput decoder hardware. However, GaB suffers from poor error-correction performance. We introduce a
Probabilistic GaB (PGaB) algorithm that disturbs the decisions made during the decoding iterations randomly with a probability value
determined based on experimental studies. We propose a heuristic that switches the decoding from GaB to PGaB after certain number of
iterations, and show that our heuristic reduces the average iteration count by up to 62% compared to GaB. We evaluate the hardware
performance and resource requirement trends of PGaB over three quasi cyclic codes using the Xilinx Virtex-6 Field Programmable Gate
Array (FPGA). We extend this analysis to performance comparison over our implementations of Gradient Descent Bit Flipping (GDBF)
and Probabilistic Gradient Descent Bit Flipping (PGDBF) algorithms for each code studied in this paper. We achieve up to four orders of
magnitude better error correction performance than the GaB with less than 1% loss in throughput performance. Our heuristic consistently
results with an improvement in maximum operational clock rate across all codes compared to the GDBF and PGDBF