Time behavioral model for phase-domain ADPLL based frequency synthesizer

C. Joubert (1) , J.F. Bercher (2) , G. Baudoin (2) , T. Divel , S. Ramet (1) , P. Level (1)

1 ST-GRENOBLE - STMicroelectronics [Grenoble]
2 ESYCOM - Electronique, Systèmes de communication et Microsystèmes

In this paper, we present a time behavioral model of a recently proposed phase-domain all-digital phase-locked loop (ADPLL) for RF applications. This model can be easily implemented, and results in a versatile and fast ADPLL simulator that enables to study many aspects of the PLL, e.g. transient responses, steady states, limit cycles, or to perform perturbation analysis. Moreover, we present a baseband analysis that allows computing the power spectral density from the instantaneous frequency obtained as the output of the behavioral model. Simulations illustrate the effectiveness of this new behavioral model.

Mots clés: Frequency synthesizers; Phase locked loops; Computational modeling; Radio frequency; Analytical models; Transient analysis; Steady-state; Limit-cycles; Performance analysis; Baseband

Domaines: Sciences de l'ingénieur [physics]; Electronique

C. Joubert, J.F. Bercher, G. Baudoin, T. Divel, S. Ramet, et al.. Time behavioral model for phase-domain ADPLL based frequency synthesizer. 2006 IEEE Radio and Wireless Symposium, Oct 2006, San Diego, United States. ⟨10.1109/RWS.2006.1615121⟩. ⟨hal-01723105⟩