Performance and layout effects of SiGe channel in 14nm UTBB FDSOI: SiGe-first vs. SiGe-last integration

Rémy Berthelon (1) , F. Andrieu (2) , P. Perreau (2) , E. Baylac (1) , A. Pofelski (1) , E. Josse (1) , D. Dutartre (1) , Alain Claverie (3) , M. Haond (1)

1 ST-CROLLES - STMicroelectronics [Crolles]
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
3 CEMES-MEM - Matériaux et dispositifs pour l'Electronique et le Magnétisme

We report on the layout effects in strained SiGe channel FDSOI pMOSFETS down to 20nm gate length. Two SiGe integration schemes are compared: the SiGe-first approach, with Ge-enrichment performed prior to the STI module and the SiGe-last approach using only a SiGe epitaxy after the STI module. We evidence reduced layout effects in the SiGe-last integration featuring Si/SiGe bilayer. SiGe-last shows -39% mobility for 170nm narrow 2μm long channel, but +21% Ieff at Lg=20nm and gate-to-STI distance of 59nm. It is translated into a -15% delay reduction for ring oscillators of 1-finger inverters. Layout dependences are explained by physical strain measurements and reproduced by a stress-based electrical model. © 2016 IEEE.

Mots clés: Germanium; Integration; Reconfigurable hardware; Solid state devices; Strain; Delay reduction; Electrical modeling; FDSOI; Integration scheme; Layout dependences; layout effects; Ring oscillator; SiGe; Silicon alloys

Domaines: Physique [physics]

Rémy Berthelon, F. Andrieu, P. Perreau, E. Baylac, A. Pofelski, et al.. Performance and layout effects of SiGe channel in 14nm UTBB FDSOI: SiGe-first vs. SiGe-last integration. Solid-State Device Research Conference (ESSDERC), 2016 46th European, 2016, Unknown, Unknown Region. pp.127-130, ⟨10.1109/ESSDERC.2016.7599604⟩. ⟨hal-01719492⟩