On the use of a localized STRASS technique to obtain highly tensile strained Si regions in advanced FDSOI CMOS devices

A. Bonnevialle (1) , S. Reboh (2) , C. Le Royer (2) , Y. Morand (1) , J.-M. Hartmann (2) , D. Rouchon (2) , J.-M. Pedini (1) , C. Tabone (2) , N. Rambal (2) , A. Payet (2, 1) , C. Plantier (2) , F. Boeuf (1) , M. Haond (1) , Alain Claverie (3) , M. Vinet (2)

1 ST-CROLLES - STMicroelectronics [Crolles]
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
3 CEMES-MEM - Matériaux et dispositifs pour l'Electronique et le Magnétisme

Strain boosters are an effective way to improve performances in advanced CMOS FDSOI devices. Hole mobility is higher in pFETs with compressive channels. Meanwhile, electron mobility is higher for nFETs with tensile channels. We present an alternative technique to blanket sSOI substrates. The efficiency of the “Strained Silicon by Top Recrystallization of Amorphized SiGe on SOI” technique has been previously successfully demonstrated on blanket SOI (+ 1.6 GPa tensile strain achieved). Here we demonstrate a simple and efficient STRASS module integration in an advanced FDSOI route (14 nm design rules) which allows to cointegrate tensile Si for nFETs and unchanged pFETs. After pFETs have been protected (SiN), the STRASS technique has been used in the SOI nFET patterns. This process requires SiGe selective epitaxy, buried amorphization by ion implantation, recrystallization and SiGe removal. Raman spectroscopy is used to characterize the stress in Si areas with respect to process conditions (implantation, active area dimensions). Moreover, the mechanisms of SiGe relaxation will be discussed as function of device dimensions and SiGe layer properties (thickness, Ge content). We demonstrate the successful integration of localized STRASS module: tensile Si patterns (for nFETs) with a level of stress of + 1.6 GPa, cointegrated with unmodified pFETs. (© 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim). Copyright © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Mots clés: CMOS integrated circuits; Germanium; Hole mobility; Ion implantation; Recrystallization (metallurgy); Silicon; Silicon alloys; Silicon nitride; Strained silicon; Advanced CMOS; CMOS devices; Fd-soi devices; FDSOI-strain-tensile stress-STRASS; Improve performance; Module integration; Process condition; Selective epitaxy; Tensile strain

Domaines: Physique [physics]

A. Bonnevialle, S. Reboh, C. Le Royer, Y. Morand, J.-M. Hartmann, et al.. On the use of a localized STRASS technique to obtain highly tensile strained Si regions in advanced FDSOI CMOS devices. physica status solidi (c), 2016, 13 (10-12), pp.740-745. ⟨10.1002/pssc.201600028⟩. ⟨hal-01719490⟩