Efficient Parametric Identification for STL

Alexey Bakhirkin (1) , Thomas Ferrère (2) , Oded Maler (1)

1 VERIMAG - IMAG - VERIMAG
2 IST Austria - Institute of Science and Technology [Klosterneuburg, Austria]

We describe a new algorithm for the parametric identification problem for signal temporal logic (STL), stated as follows. Given a dense-time real-valued signal w and a parameterized temporal logic formula phi, compute the subset of the parameter space that renders the formula satisfied by the signal. Unlike previous solutions, which were based on search in the parameter space or quantifier elimination, our procedure works recursively on phi and computes the evolution over time of the set of valid parameter assignments. This procedure is similar to that of monitoring or computing the robustness of phi relative to w. Our implementation and experiments demonstrate that this approach can work well in practice.

Mots clés: Signal Temporal Logic; Parametric temporal Logic; Parametric Identification

Domaines: Autre [cs.OH]

Alexey Bakhirkin, Thomas Ferrère, Oded Maler. Efficient Parametric Identification for STL. 21st International Conference on Hybrid Systems: Computation and Control (HSCC'18), Apr 2018, Porto, Portugal. pp.177-186, ⟨10.1145/3178126.3178132⟩. ⟨hal-01715564v4⟩