Thousand core chips, Proceedings of the 44th annual conference on Design automation, DAC '07, pp.746-749, 2007. ,
DOI : 10.1145/1278480.1278667
Design space exploration of high level stream programs on parallel architectures: A focus on the buffer size minimization and optimization problem, 2013 8th International Symposium on Image and Signal Processing and Analysis (ISPA), pp.738-743, 2013. ,
DOI : 10.1109/ISPA.2013.6703835
Enabling the Heterogeneous Accelerator Model on Ultra-Low Power Microcontroller Platforms, Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.1201-1206, 2016. ,
DOI : 10.3850/9783981537079_0626
A clustered manycore processor architecture for embedded and accelerated applications, 2013 IEEE High Performance Extreme Computing Conference (HPEC), pp.1-6, 2013. ,
DOI : 10.1109/HPEC.2013.6670342
PiMM: Parameterized and Interfaced dataflow Meta-Model for MPSoCs runtime reconfiguration, 2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), pp.41-48, 2013. ,
DOI : 10.1109/SAMOS.2013.6621104
URL : https://hal.archives-ouvertes.fr/hal-00877492
Hardware-dependent Software, 2009. ,
DOI : 10.1007/978-1-4020-9436-1_1
SigmaC: A programming model and language for embedded manycores, Algorithms and Architectures for Parallel Processing, ser. Lecture Notes in Computer Science, pp.385-394, 2011. ,
Asynchronous one-sided communications and synchronizations for a clustered manycore processor, Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia , ESTIMedia '17, 2017. ,
DOI : 10.1109/CODESISSS.2015.7331385
Hierarchical Dataflow Model for efficient programming of clustered manycore processors, 2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2017. ,
DOI : 10.1109/ASAP.2017.7995270
Spider: A Synchronous Parameterized and Interfaced Dataflow-based RTOS for multicore DSPS, 2014 6th European Embedded Design in Education and Research Conference (EDERC), pp.167-171, 2014. ,
DOI : 10.1109/EDERC.2014.6924381
URL : https://hal.archives-ouvertes.fr/hal-01067052
High-performance algorithms for compile-time scheduling of parallel processors, 1997. ,
Synchronous data flow, Proceedings of the IEEE, vol.75, issue.9, pp.1235-1245, 1987. ,
DOI : 10.1109/PROC.1987.13876
Dataflow process networks, Proceedings of the IEEE, pp.773-801, 1995. ,
DOI : 10.1109/5.381846
URL : http://ptolemy.eecs.berkeley.edu/papers/95/processNets/proceedings.pdf
Evaluation of Synchronous Dataflow Graph Mappings onto Distributed Memory Architectures, 2016 Euromicro Conference on Digital System Design (DSD), pp.146-153, 2016. ,
DOI : 10.1109/DSD.2016.52
URL : https://hal.archives-ouvertes.fr/hal-01444593
Hierarchical reconfiguration of dataflow models, Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04., 2004. ,
DOI : 10.1109/MEMCOD.2004.1459852
Epiphany-v: a 1024 processor 64-bit risc system-on-chip, 2016. ,
ActorX10: an actor library for X10, Proceedings of the 6th ACM SIGPLAN Workshop on X10, X10 2016, pp.24-29, 2016. ,
DOI : 10.1145/2246056.2246057
Stream Drive, Proceedings of the Computing Frontiers Conference on ZZZ , CF'17, pp.1-8, 2017. ,
DOI : 10.1007/s11227-010-0503-2