Track finding mezzanine for Level-1 triggering in HL-LHC experiments
Résumé
The increase of the luminosity in the High Luminosity upgrade of the CERN Large Hadron Collider (HL-LHC) will require the use of Tracker information in the evaluation of the Level-1 trigger in order to keep the trigger rate acceptable (i.e.: <;1MHz). In order to extract the track information within the latency constraints (<;5μs), a custom real-time system is necessary. We developed a prototype of the main building block of this system, the Pattern Recognition Mezzanine (PRM) that combines custom Associative Memory ASICs with modern FPGA devices. The architecture, functionality and test results of the PRM are described in the present work.
Mots clés
Field programmable gate arrays
Pattern recognition
Associative memory
Roads
Real-time systems
Poles and towers
application specific integrated circuits
content-addressable storage
field programmable gate arrays
trigger circuits
track finding mezzanine
level-1 triggering
HL-LHC experiments
high luminosity upgrade
CERN large hadron collider
tracker information extraction
latency constraints
real-time system
pattern recognition mezzanine
PRM
associative memory ASICs
FPGA devices
Trigger circuits
Pattern matching
Associative Memory
Real time systems
FPGAs
Application specific integrated circuits
CERN LHC Coll
integrated circuit
trigger
track data analysis
FPGA
electronics: design