A low-power and high-density Associative Memory in 28 nm CMOS technology

Abstract : In this paper we present a new Associative Memory (AM) chip designed in the 28 nm TSMC HPL technology. Two of the main characteristics of the new chip are reduced power consumption and an increased memory cell area density by the use of two newly designed memory cell technologies. The aim of the new chip is to test the new technologies with realistic front-end functions. The integration of the AM and FPGA is also enhanced. In addition, LVDS drivers and receivers are implemented to strengthen the signal integrity of the I/Os. The new AM chip design is submitted for the fabrication. The die will be packaged in a 17 × 17 Ball Grid Array (BGA) standalone package with a Silicon In Package (SiP) structure mounting AM dies and a bare die FPGA.
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Communication dans un congrès
6th International Conference on Modern Circuits and Systems Technologies, May 2017, Thessaloniki, Greece. pp.7937632, 2017, 〈10.1109/MOCAST.2017.7937632〉
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https://hal.archives-ouvertes.fr/hal-01669639
Contributeur : Inspire Hep <>
Soumis le : mercredi 20 décembre 2017 - 23:49:27
Dernière modification le : mardi 25 septembre 2018 - 22:10:29

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Alberto Annovi, Giovanni Calderini, Francesco Crescioli, Francesco De Canio, Luca Frontini, et al.. A low-power and high-density Associative Memory in 28 nm CMOS technology. 6th International Conference on Modern Circuits and Systems Technologies, May 2017, Thessaloniki, Greece. pp.7937632, 2017, 〈10.1109/MOCAST.2017.7937632〉. 〈hal-01669639〉

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