A low-power and high-density Associative Memory in 28 nm CMOS technology
Résumé
In this paper we present a new Associative Memory (AM) chip designed in the 28 nm TSMC HPL technology. Two of the main characteristics of the new chip are reduced power consumption and an increased memory cell area density by the use of two newly designed memory cell technologies. The aim of the new chip is to test the new technologies with realistic front-end functions. The integration of the AM and FPGA is also enhanced. In addition, LVDS drivers and receivers are implemented to strengthen the signal integrity of the I/Os. The new AM chip design is submitted for the fabrication. The die will be packaged in a 17 × 17 Ball Grid Array (BGA) standalone package with a Silicon In Package (SiP) structure mounting AM dies and a bare die FPGA.
Mots clés
Cams
Clocks
Analytical models
Large Hadron Collider
Circuits and systems
Associative memory
Computer architecture
ball grid arrays
CMOS memory circuits
field programmable gate arrays
low-power electronics
memory architecture
power consumption
low-power associative memory
high-density associative memory
CMOS technology
reduced power consumption
memory cell area density
FPGA
LVDS drivers
AM chip design
ball grid array standalone package
silicon in package
size 28 nm
density
electronics
fabrication
integrated circuit: design