Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations

Abstract : Yield estimation is an indispensable piece of information at the onset of high-volume production of a device, as it can inform timely process and design refinements in order to achieve high yield, rapid ramp-up, and fast time-to-market. To date, yield estimation is generally performed through simulation-based methods. However, such methods are not only very time-consuming for certain circuit classes, but also limited by the accuracy of the statistical models provided in the process design kits (PDKs). In contrast, herein we introduce yield estimation solutions which rely exclusively on silicon measurements and we apply them toward predicting yield during: 1) production migration from one fabrication facility to another and 2) transition from one design generation to the next. These solutions are applicable to any circuit, regardless of PDK accuracy and transistor-level simulation complexity, and range from rather straightforward to more sophisticated ones, capable of leveraging additional sources of silicon data. Effectiveness of the proposed yield forecasting methods is evaluated using actual high-volume production data from two 65-nm RF transceiver devices.
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Contributor : Haralampos Stratigopoulos <>
Submitted on : Wednesday, December 20, 2017 - 6:33:05 PM
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Ali Ahmadi, Haralampos-G. Stratigopoulos, Ke Huang, Amit Nahar, Bob Orr, et al.. Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2017, 36 (12), pp.2120-2133. ⟨10.1109/TCAD.2017.2669861⟩. ⟨hal-01669356⟩



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