Construction of an Integrated Circuit Emission Model of a FPGA

Chaimae Ghfiri (1, 2) , André Durier (1) , Alexandre Boyer (2) , Sonia Ben Dhia (2) , Christian Marot (3)

1 IRT Saint Exupéry - Institut de Recherche Technologique
2 LAAS - Laboratoire d'analyse et d'architecture des systèmes
3 Airbus Defence and Space [Taufkirchen]

This paper describes the construction flow and the validation of an equivalent conducted emission model of a complex integrated circuit (a FPGA), based on the ICEM modelling approach.

Mots clés: Integrated circuits; Modeling; Conducted emission; ICEM; FPGA

Domaines: Réseaux et télécommunications [cs.NI]; Electronique

Chaimae Ghfiri, André Durier, Alexandre Boyer, Sonia Ben Dhia, Christian Marot. Construction of an Integrated Circuit Emission Model of a FPGA. APEMC 2016 (7th Asia Pacific International Symposium on Electromagnetic Compatibility & Signal Integrity), May 2016, Shenzhen, China. pp. 402-405. ⟨hal-01663667v1⟩