A 65-nm CMOS 7fJ per synaptic event clique-based neural network in scalable architecture

Benoit Larras (1) , Paul Chollet (2, 3, 4) , Cyril Lahuec (2, 3, 4) , Fabrice Seguin (2, 3, 4) , Matthieu Arzel (2, 3, 4)

1 IEMN - Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520
2 Lab-STICC_IMTA_CACS_IAS
3 ELEC - Département Electronique
4 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance

Clique-based neural networks are less complex than commonly used neural network models. They have a limited connectivity and are composed of simple functions. They are thus adapted to implement neuro-inspired computation units operating under severe energy constraints. This paper shows an ST 65-nm CMOS ASIC implementation for a 30-neuron cliquebased neural network circuit. With a 0.8V power supply and 150nA unitary current, the neuron energy consumption is only 7fJ per synaptic event, i.e. 1330 times less energy than a state-ofthe-art neuron. The network occupies a 41,820µm² silicon area.

Mots clés: CMOS analogue integrated circuits; Neural Networks

Domaines: Electronique; Traitement du signal et de l'image [eess.SP]

Benoit Larras, Paul Chollet, Cyril Lahuec, Fabrice Seguin, Matthieu Arzel. A 65-nm CMOS 7fJ per synaptic event clique-based neural network in scalable architecture. ISCAS 2017 : IEEE International Symposium on Circuits and Systems, May 2017, Baltimore, United States. pp.1 - 4, ⟨10.1109/ISCAS.2017.8050658⟩. ⟨hal-01656139⟩