Metastability-Aware Memory-Efficient Time-to-Digital Converters

Matthias Függer 1, 2, 3 Attila Kinali 4 Christoph Lenzen 4 Thomas Polzer 5
3 MEXICO - Modeling and Exploitation of Interaction and Concurrency
LSV - Laboratoire Spécification et Vérification [Cachan], ENS Cachan - École normale supérieure - Cachan, Inria Saclay - Ile de France, CNRS - Centre National de la Recherche Scientifique : UMR8643
Abstract : We propose a novel method for transforming delay-line time-to-digital converters (TDCs) into TDCs that output Gray code without relying on synchronizers. We formally prove that the inevitable metastable memory upsets (Marino, TC'81) do not induce an additional time resolution error. Our modified design provides suitable inputs to the recent metastability-containing sorting networks by Lenzen and Medina (ASYNC'16) and Bund et al. (DATE'17). In contrast, employing existing TDCs would require using thermometer code at the TDC output (followed by conversion to Gray code) or resolving metastability inside the TDC. The former is too restrictive w.r.t. the dynamic range of the TDCs, while the latter loses the advantage of enabling (accordingly much faster) computation without having to first resolve metastability. Our all-digital designs are also of interest in their own right: they support high sample rates and large measuring ranges at nearly optimal bit-width of the output, yet maintain the original delay-line's time resolution. No previous approach unifies all these properties in a single device.
Type de document :
Communication dans un congrès
IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2017, San Diego, United States
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Contributeur : Matthias Függer <>
Soumis le : jeudi 30 novembre 2017 - 16:44:35
Dernière modification le : jeudi 11 janvier 2018 - 06:27:34


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  • HAL Id : hal-01652787, version 1


Matthias Függer, Attila Kinali, Christoph Lenzen, Thomas Polzer. Metastability-Aware Memory-Efficient Time-to-Digital Converters. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2017, San Diego, United States. 〈hal-01652787〉



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