A 14-b Two-step Inverter-based Σ∆ ADC for CMOS Image Sensor

Pierre Bisiaux (1) , Caroline Lelandais-Perrault (1) , Anthony Kolar (1) , Philippe Benabes (1) , Filipe Vinci dos Santos (2)

1 GeePs - Laboratoire Génie électrique et électronique de Paris
2 Chaire Conception Analogique Avancée Thales/Supélec

This paper presents a 14-bit Incremental Sigma Delta (IΣ∆) analog-to-digital converter (ADC) suitable for a column wise integration in a CMOS image sensor. A two-step conversion is performed to improve the conversion speed. As the same Σ∆ modulator is used for both steps, the overall complexity is reduced. Furthermore, the use of inverter-based amplifiers instead of operational transconductance amplifier (OTA) facilitates the integration within the column pitch and decreases power consumption. The proposed ADC is designed in 0.18 µm CMOS technology. The simulation shows that for a 1.8 V voltage supply, a 20 MHz clock frequency and an oversampling ratio (OSR) of 70, the power consumption is 460 µW, achieving an SNR of 83.7 dB.

Mots clés: sigma-delta (Σ∆); incremental; ADC; CMOS Image Sensor; two-step; column-parallel; inverter-based

Domaines: Electronique

Pierre Bisiaux, Caroline Lelandais-Perrault, Anthony Kolar, Philippe Benabes, Filipe Vinci dos Santos. A 14-b Two-step Inverter-based Σ∆ ADC for CMOS Image Sensor. 2017 15th IEEE International New Circuits and Systems Conference (NEWCAS) , Jun 2017, strasbourg, France. ⟨10.1109/NEWCAS.2017.8010144⟩. ⟨hal-01646639⟩