Fully Depleted SOI Characterization by Capacitance Analysis of p-i-n Gated Diodes

Carlos Navarro (1) , Mayline Bawedin (2, 3) , François Andrieu (4) , Jacques Cluzel (4) , Sorin Cristoloveanu (1)

1 IMEP-LAHC - Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation
2 IES - Institut d’Electronique et des Systèmes
3 M@CSEE - Micro électronique, Composants, Systèmes, Efficacité Energétique
4 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information

Split capacitance measurements in thin SOI p-i-n gated diodes are performed and discussed. Contrarily to MOSFETs, the n + and p + contacts of the diode supply instantly minority and majority carriers preventing parasitic deep-depletion and transient effects. The gated diode enables accurate characterization from accumulation to strong inversion. We demonstrate that the diode capacitance curves provide extensive information, such as layer thickness and threshold voltage for both n- and p-type MOSFETs simultaneously. The experimental results are validated and explained through numerical simulations.

Mots clés: threshold voltage; SOI; p-i-n; gated diode; inter-gate coupling; Capacitance; film thickness

Domaines: Electronique

Carlos Navarro, Mayline Bawedin, François Andrieu, Jacques Cluzel, Sorin Cristoloveanu. Fully Depleted SOI Characterization by Capacitance Analysis of p-i-n Gated Diodes. IEEE Electron Device Letters, 2015, 36 (1), pp.5 - 7. ⟨10.1109/LED.2014.2368596⟩. ⟨hal-01644390⟩