L. Benini and G. Micheli, Networks on chips: a new SoC paradigm, Computer, vol.35, issue.1, pp.70-78, 2002.
DOI : 10.1109/2.976921

URL : https://infoscience.epfl.ch/record/165542/files/00976921.pdf

J. Y. Hur, S. Wong, and S. Vassiliadis, Partially reconfigurable pointto-point interconnects in virtex-ii pro fpgas, International Workshop on Applied Reconfigurable Computing, pp.49-60, 2007.
DOI : 10.1007/978-3-540-71431-6_5

URL : http://ce.et.tudelft.nl/publicationfiles/1274_479_ARC07_P2P_Hur.pdf

V. Cyclone and . Handbook, Device Interfaces and Integration, Intel Altera, vol.1, pp.2016-2022, 2016.

D. Koch, Partial Reconfiguration on FPGAs: Architectures, Tools and Applications, 2012.
DOI : 10.1007/978-1-4614-1225-0

L. Devaux, S. B. Sassi, S. Pillement, D. Chillet, and D. Demigny, Flexible interconnection network for dynamically and partially reconfigurable architectures, International Journal of Reconfigurable Computing, vol.2010, p.6, 2010.
DOI : 10.1155/2010/390545

URL : https://hal.archives-ouvertes.fr/inria-00437763

C. Bobda and A. Ahmadinia, Dynamic Interconnection of Reconfigurable Modules on Reconfigurable Devices, IEEE Design and Test of Computers, vol.22, issue.5, pp.443-451, 2005.
DOI : 10.1109/MDT.2005.109

S. Jovanovic, C. Tanougast, S. Weber, and C. Bobda, CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs, 2007 International Conference on Field Programmable Logic and Applications, pp.753-756, 2007.
DOI : 10.1109/FPL.2007.4380761

T. Pionteck, R. Koch, and C. Albrecht, Applying Partial Reconfiguration to Networks-On-Chips, 2006 International Conference on Field Programmable Logic and Applications, pp.1-6, 2006.
DOI : 10.1109/FPL.2006.311208

P. Marquet, S. Duquennoy, S. L. Beux, S. Meftali, and J. Dekeyser, Massively parallel processing on a chip, Proceedings of the 4th international conference on Computing frontiers , CF '07, pp.277-286, 2007.
DOI : 10.1145/1242531.1242571

URL : https://hal.archives-ouvertes.fr/hal-00688418

S. Young, P. Alfke, C. Fewer, S. Mcmillan, B. Blodget et al., A high I/O reconfigurable crossbar switch, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003., pp.3-10, 2003.
DOI : 10.1109/FPGA.2003.1227236

C. H. Hoo and A. Kumar, An area-efficient partially reconfigurable crossbar switch with low reconfiguration delay, 22nd International Conference on Field Programmable Logic and Applications (FPL)
DOI : 10.1109/FPL.2012.6339136

A. Morales-villanueva and A. Gordon-ross, Partial Region and Bitstream Cost Models for Hardware Multitasking on Partially Reconfigurable FPGAs, 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, pp.90-96, 2015.
DOI : 10.1109/IPDPSW.2015.148