Accurate static timing analysis for deep submicronic CMOS circuits

Karim Dioury; Alain Greiner; Marie-Minerve Rosset-Louërat

doi:10.1007/978-0-387-35311-1_36

Conference papers

Accurate static timing analysis for deep submicronic CMOS circuits

Karim Dioury ¹ Alain Greiner ¹ Marie-Minerve Rosset-Louërat ¹

1 ASIM - Architecture des Systèmes intégrés et Micro électronique

LIP6 - Laboratoire d'Informatique de Paris 6

Abstract : This paper presents the performance of the static timing analyzer TAS for deep sub-micronic CMOS technologies. The methodology used by TAS is given with special emphasis on its Short Channel MOS model. Results are given to show the accuracy of the static timing analyzer TAS for various CMOS circuits (including pass transistor and precharge logic) as well as for various CMOS processes ranging from 1.2μ to 0.35μ. The Short Channel MOS model of TAS appears to be relevant to the analysis of deep submicronic processes.

Document type :

Conference papers

Domain :

Computer Science [cs]

Complete list of metadatas

https://hal.archives-ouvertes.fr/hal-01627845
Contributor : Lip6 Publications <>
Submitted on : Thursday, November 2, 2017 - 2:39:46 PM
Last modification on : Friday, January 8, 2021 - 5:32:05 PM

Accurate static timing analysis for deep submicronic CMOS circuits

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Accurate static timing analysis for deep submicronic CMOS circuits

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