An FPGA stereo matching unit based on fuzzy logic

Abstract : The stereo matching is one of the most widely used algorithms in real-time image processing applications such as positioning systems for mobile robots, three-dimensional building mapping and both recognition, detection and three-dimensional reconstruction of objects. In order to improve the runtime, stereo matching algorithms often have been implemented in dedicated hardware such as FPGA or GPU devices. In this article an FPGA stereo matching unit based on fuzzy logic is described. The proposed method consists of three stages: first, three similarity parameters inherent to each pixel contained in the input stereo pair are determined; later, these parameters are submitted to a fuzzy inference system that determines a value of fuzzy-similarity; finally, the disparity value is determined as the index for the maximum value of the fuzzy-similarity values (zero up to d max). Dense disparity maps are computed at a rate of 76 frames per second for input stereo pairs of 1280x1024 pixel resolution and a maximum expected disparity equal to 15. The developed FPGA architecture provides reduction of the hardware resource demand; up to 67,384, minimum 9,788 for logic units, up to 35,475, minimum 11,766 for bits of memory. Increases the processing speed; up to 78,725,120, minimum 14,417,920 pixels per second and outperforms the accuracy level of most of real-time stereo matching algorithms reported in the literature.
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Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2016, 42, pp.87-99. 〈10.1016/j.micpro.2015.10.011〉
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M. Pérez-Patricio, Abiel Aguilar-González, M. Arias-Estrada, H. Hernández-De León, J. Camas-Anzueto, et al.. An FPGA stereo matching unit based on fuzzy logic. Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2016, 42, pp.87-99. 〈10.1016/j.micpro.2015.10.011〉. 〈hal-01627651〉

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